Has anyone implemented the SPI bus on a 7831R using Labview 2009? I

[Eletrostatic]

Yes I get the same result no matter how much (or little) I change those Wait Tick values

I will change some of the logic inside the code to see if it makes any differance.

[Eletrostatic]

Having some issues understanding how this works....

Wait Ticks is based on the Clock used. But wait count should be the amount of clocks to wait before and after the CS is asserted / deasserted., right?! But it makes no differance what I set the clock count too. Its always the same issue... 

[Eletrostatic]

So today I tried the example FPGA SPI MASTER (SCTL) from here http://zone.ni.com/devzone/cda/epd/p/id/3458

I added extra wait states for the transitions between the CS and SCLK and seems to work fine. However, how do I include the MISO support (Reading from the slave) for this example? If this all works fine I will just make a DMA and fifos to the HOST.VI and job done 😉

Thanks for any help

[smithd]

It looks like you just need to add another case for the MISO and then write data to the MISO line when SCLK is high. Looking at FPGA SPI Master in that example you posted seems to indicate how it needs to be done.

Thanks,

D Smith

[Eletrostatic]

Just clarify your comment "then write data to the MISO line when SCLK is high" Do you mean when the SCLK is active? During the times its high?

Thanks in advance....

[smithd]

Yeah, active and high. My understanding of SPI is that it should be pulling in data and shooting out data at the same time, while the sclk is active, on each rising edge. So if you change the data when you change the SCLK, you know which bit is being sent or recieved.

[Eletrostatic]

Hi,

I tried added the MISO and simulation looks ok. But do not get any data when I loop MOSI and MISO togethor. Could you please look at my code and edit it so that it works. Been struggling a day trying to get this working, Really need to get the SPI up and working ASAP. Thanks...

[Eletrostatic]

Hi,

Well I got the MISO integrated and works. Kind off. For some reason when I simulate its fine. But if I run the code on the target it adds bits!! Input=1, output=4, input=2, output=8 and so on.

[smithd]

What do you mean when you say simulation? Do you use a custom VI to handle the data? Are you using run on development computer with real I/O?

If I understand correctly, you are outputting 00000001 and you get back 00000100, or 0010 and you get back 1000, right? So you are sending 2 false bits more than you wanted, either before or after the rest of your data. Do you know which one it is? Another important question: my understanding of SPI was that it fires on a rising edge, yet yours seems to read data on the falling edge. Is that your intent? Another thing to look out for is race conditions--the FPGA is much faster, which may explain why the simulation is working but the FPGA is not. Perhaps add a few sequence structures to your code, to make sure everything happens in exactly the right order.

Past those points, I can't see anything clearly wrong with your code. Just make sure you are following the protocol properly as I described above. When things are happening at 5 MHz, you cannot be too careful about timing.

Thanks

[Eletrostatic]

Hi, Could you please edit the code too what you think it should be. Really stuck on this issue....Thanks