NI9237 rate instable

[Mugur]

Hi everyone

I'm building up an application for continuous datalogging using the CompactRIO platform (controller 9002, chassis 9101) with channels from 3 modules: 9201, 9401, 9237.

The problem I'm experiencing is that every 2 seconds or so the timed loop appears to execute an extra iteration and therefore increasing the number of values in the DMA.

When reading a fix number of values in the RT app the 'elements remaining' continue to build up endlessly.

I've tried to troubleshoot the problem and when the NI9237 channels are not included in the FPGA app the loop runs spot on the desired rate. As soon as I introduce the 9237 channels the loop behaves unpredictable.

Any ideas how to fix this issue?

Many thanks,

Mugur

[Texas_Diaz]

It sounds from your descriptions that when you add the acquisition of the 9237 that your loop rates exceed the programmed loop rate.  How often are your loops exceeding the loop period (i.e. "running late")?  You cannot generally change how long it takes for the stuff in the loop to run (without rearchitecting the loop contents themselves), but you can profile the loop to determine if you're occasionally running late (or always as the case may be).  Use the internal cluster inside the Timed Loop to determine if your loop is actually running late - you may find your loop execution period is too small for the amount of work you want to do.

-Danny 

[Mugur]

Hi Danny

Thanks for your promptitude.

in the FPGA code I'm actually using the while loop with the loop timer not a timed loop as I infered earlier. Apologies for confusion.

The loop is very basic and only contains the IO nodes and the DMA function, all this at a rate of 0.5 ms (2000Hz on the NI9237) which is on the slow side of DAQ.

A way of recovering the missing elements is that on the RT I read the no of elements in the FIFO and then read from FIFO itself. But this is just a work-around and I was more interested in a genuine solution.

I have concerns about the continuity of the data. I will have to connect the system to some sort of function generation to see is I'm missing anythig from the 'real' signal.

Mugur

[Texas_Diaz]

Understand that you ARE using a cRIO-9002 with a sub-200MHz processor and likely an older FPGA - that's definitely on the slow side of DAQ as well.  🙂  Have you timed the FPGA side to ensure you get data fast enough?

-Danny

[Mugur]

Danny

It is a pretty basic application and I wouldn't bin the hardware. I guess that I'm a bit of a hoarder when it comes to NI stuff.

The data can be acquired at rates far higher. I've tried both LV10 and 11 to see if there is any difference. None observed.

The module has a built in clock so the FPGA and controller spec should not matter that much. It behaves as if the module acquires data at a rate of some 2000.5 Hz instead of 2000Hz. It could be within the module's accuracy.

I'm testing a workaround this week but I'd still like to know where the problem originates.

Mugur