Pass 'For Loop' Value before Loop finishes - FPGA

[bones349]

Hello,

LV 8.5, LV FPGA, PCI 7831-R FPGA Board

I've got a brain cramp on this one.  I have a function (Arb. Sig Read) which Im using to generate an arbitrary signal which I've created in Memory.  I can't seem to pass out the Data value however.  I know why I can't, its because it is nested in a 'For Loop' that runs indefinetly and only updates the value each time it loops back to 'zero'.  Any quick and dirty ideas on how to use this value as it is being updated in the For loop in my Main vi?

I've seen posts on using 'queues', property nodes, and local variable, but I just cant make sense of them.  Maybe because this is FPGA, something is different/not supported?

** My main is "MicroMirror Control Arb. SP", look in case #4, and the "False" condition**

The 'subVI' is called "Arb Sig Read RevB", and I'm trying to pass the 'Data' variable to the main while the For Loop still runs.

Thanks!

[bones349]

Sorry.. attachements

[bones349]

FYI, my Memory Read/Write functions were taking from this example: 

Arbitrary Waveform Generation with LabVIEW FPGA (Memory Read and Write)

http://zone.ni.com/devzone/cda/epd/p/id/447

Basically, in the Read_Write_Memory(fpga).vi, I want to pass the output Data to another VI, instead of just the Analog Out.

Thanks

[AdnanZ]

Use target–scoped FIFOs if you want to create a single FIFO that you can use in multiple VIs. You also can use target–scoped FIFOs to transfer data from one subVI to another in an FPGA VI. Right-click on your FPGA Target and navigate to New -> FIFO.

[bones349]

Thanks Adnan Z,

I added the Target-Scoped FIFO to the FPGA code, and it tested fine when I ran it in simulation.

I've now run into a problem when I compiled it, and run it with the host.  The behavior is that I can't break from my case structure until all the FIFO elements have been read.  I'm thinking I dont completely understand the 'timeout' value for these FIFOs, can someone please help me out?

This Target Scoped FIFO has a depth of 1024, and I have set the timeout to '0' for both the read and write. (The Write is found in 'Arb Sig Read Rev B.vi' in the TRUE condition, the Read is found in 'MicroMirror Control Arb. SP.vi  case#4, TRUE condition).

When I write to the FIFO, Im only adding 4-5 elements total, and they are being written about 1 every second (time delay).  Im confused on whether I should be using a '0' FIFO timeout, or a '-1'??

[bones349]

One more thing:  My Target-to-Host FIFOs "FIFO_1" and "FIFO_2" stop working as soon as I start reading from the Target-Scoped FIFO.

When I say, 'stop working' it means that on the Host, I no longer receive any data.

This is really confusing, because when I run the emulator on the FPGA code, all FIFO data is being updated with each iteration of the while loop.  Not sure how to troubleshoot from here.

Thanks

[AdnanZ]

Timeout inputs the number of clock ticks the function waits for available space in the FIFO if the FIFO is full. A value of –1 prevents the function from timing out. A value of 0 indicates no wait. Wire a constant of 0 to Timeout if you use the FIFO Method Node in a single-cycle Timed Loop. And, in your case, you can just leave it to the default value of 0.

I would suggest you create a simple example that highlights the issue and post the entire project over here, otherwise it becomes difficult to open the VIs and understand the issue if we are not able to see the FIFOs and the target the FPGA VIs are running on.

[bones349]

Thanks for the advice.  I realized my problem was that I had a FIFO being read on the host that had a -1 timeout.  Since data was being written to it very slowly, it was waiting a long time to execute.  I changed it to a no wait '0', and that solved it.

I've run into a new problem however.  The attached code shows what I am trying to do.  The top while loop is used to write data to memory, and also read it back in a time delayed loop.  Basically Im trying to do an arbitrary signal generator, and use the 'Count (usec)' control to change the frequency.

The top loop is going to run slower because there is a time delay in the Arb Sig Read function.  Arb Sig Read is writting its data to a Target Scoped FIFO.  I want the bottom loop to run in parrallel to this, as fast as possible.  What is the best way to do this?

The way I have it now, the Target Scoped FIFO is being read in the faster bottom loop.  I read the FIFO way faster than it is being filled, therefore most of the data being read is '0'.  If I set the timeout on the FIFO to '-1', then the data read is correct, but now the bottom loop slows down to the speed of the top loop.

Do I need an interrupt in the top loop to signal the bottom loop that there is a value ready to be read? 

Thanks alot!!!

[Donovan_B]

You can set the timeout to 0 and monitor the Timed Out? terminal on the FIFO Read.  If the function does not time out, then there is data in the FIFO that you can read and then output and send to your other FIFO.  If the Timed Out? terminal is true, don't output another value to the AO or write to the other FIFO.  You just need a case structure to determine what to do.  This will let your bottom loop run as fast as possible and only output new data when it is available.

Message Edited by Donovan B on 11-03-2009 11:32 AM

[bones349]

Donovan,

Thanks for the reply.

I think you have me on the right track.  I want to have my Target->Host FIFO and Analog Out being updated every interation of the while loop however.  I think I want to do something like in this picture... but not sure how to do it.

Basically I want to use that 'Timed Out' flag to signal that its time to update the values; otherwise keep outputing the old value.

What I have in the picture does not work because my 'True' statement is blank and is set to 'Use Default if Unwired'.

Any ideas? Thanks!