cRIO 9025/NI 9144 Data Acquisition

[bkb]

I have a cRIO 9025 and an NI 9144. I'd like to log data to the 9025's local storage at 1000Hz. While also doing this, I'm trying to setup a control loop in the FPGA. It is my understanding that you should be acquiring data in the FPGA and reading it from a real-time VI. The problem I'm having is that I'm using the FPGA in the 9025 to try and read all the channels on all modules for both chassis (16 slots total) and I cannot access the modules on the 9144.

Should I be using the scan engine instead? Can I use FPGA and Scan engine at the same time?

Thanks

[Wayne.C]

bkb,

You can use scan and FPGA at the same time.  See here .

[Joe D.]

Hi bkb,

Programming the fpga with ethercat is a little different than normal FPGA. You might want to take a look at this example 

[bkb]

So the "SCAN Engine" can do 256 channels at 1000Hz without batting an eyelash?

Why would they let you DMA data from an FPGA to the  Host and not let you do it on an expansion chassis?

What is the "standard practice" for doing what I'm trying to do?

[DirkW]

The 9144 chassis is connected to your cRIO or PXI EtherCAT master through EtherCAT Bus. Tha makes DMA impossible.

You have to use the EtherCAT bus to transfer the data and the only way to do that is through I/O variables.

For FPGA the project allows you to create User defined variable  (UDVs) thes are able to utilize the ethercat scan engine. See the examples shipping with the ethercat driver for how to.

DirkW

[jkurtw]

bkb,

No, you will not be able to acquire the 9144 channels at 1kHz. I don't know what rate you will be able to hit with the scan engine, but it will be CPU bound. There are some benchmarks, but they are for the older controllers. The 9025 should do significantly better, maybe 2x, but 256 channels at 1kHz will not be achievable. 

1kHz on your local chassis is easy when using DMA. Here is a tutorial that can walk you through that part. Make sure you look at the section on LabVIEW FPGA.

If you need to acquire 16 slots at 1kHz, you would need two synchronized 9025s or go with something like the new 14-slot MIXI-Express chassis. Although, that would require and PXI or Industrial Controller.

Kurt

[providev]

Hi,

I'm in the process of developing almost the same type of application and would like to know what are the limiting factors that prevents having a communications loop through EtherCAT running synchronized to a 1kHz scan clock?

Is it a limiting factor of how fast the Shared Variable Engine can run on a particular processor? or is it a limiting factor of the EtherCAT communications bus itself?

I've attached an image of my FPGA VI architecture and the quantity and type of the user-defined variables for your reference. I have put my user-defined variables to update and read from local variables on the FPGA, so that the I/O scan time will not limit my communication loop.

Thank you in advance for your help!

Cheers!

sankah2k

[DirkW]

The limiting factor is clearly the Scan engine running on your RT Host and LV that needs approx 6 us per I/O variable. 256 channles might get close to a kHz on a 9025 controller with LV 2009 and the advanced I/O library or LV 2010 and the new programmatic block read. However you still need some time to execute your code logic on RT and that might break the KHz loop rate.

So you should think about running a slower ECAT loop rate and perhaps do a faster FPGA acquisition rate with some pre processing of your data?

DirkW