Most likely the error is coming from one of the previous nodes in your Host VI and getting passed through to the Close FPGA VI Reference node. Can you trace the error code back and determine which node is generating the error.
I did notice that one of the I/O control nodes in Frame 1 'read done' is unwired.
Are you running the host VI in LabVIEW Windows or Real-Time?
authored byChristian L, CLA
Systems Engineering Manager - Automotive and Transportation
NI - Austin, TX

