04-23-2011 08:03 AM
Hi Stephen,
That's really a good suggestion...I missed that memory pre-allocation! I will try to make the alterations and post you the result. Thank you!
Best regards,
João Barata
05-09-2011 06:25 AM
Hi Stephen,
I have already performed the changes you have suggested. Although a reduction of a few percent on the CPU charge of the CRio 9022 was noticed, in the CRio 9074 the code still doesn’t run @1KHz. I’m getting more and more convinced this isn’t a code problem, due to the following experience I'll briefly describe:
i) when running a single timed loop @1KHz in the CRio 9074, without any code inside it, the CPU charge is already about 25%.
ii) If you add code to read from the FPGA vi’s indicators (without actually showing the indicators), the CPU charge goes to about 50%...
iii) when you add RT buffer write code the CPU charge goes up to 55%...and this is only with one timed while loop (no RT buffer read, no TCP connections to the PC!).
iv) When adding the second timed while loop code (@100Hz) for buffer read and TCP connections, the CPU charge goes to 80%...
v) In this last situation, if you make the fpga and RT code to run automatically (without showing any front panel) the cpu charge lowers to 70%...so you only get around 30% to actually implement your code! If your controller isn’t very simple, you won’t get it to work!
Anyway, thank you for your help! Best regards,
João Barata