12-15-2009 05:34 PM
Hi All,
At last I had the time to check your solution.
It works fine while running on my computer yet when I compile it to the FPGA I get an error "FPGA Xflow Compile Error 2" and the output dialog says I should lower my resources or whatever.
I am using NI-cRIO-9072.
Any suggestion?
Thanks,
Yuval
12-15-2009 05:54 PM
12-15-2009 08:15 PM
12-16-2009 07:31 AM
strange, I had the feeling it is a moving Standerd dev. Are you sure?
Anyhow, I am still not able to compile the FPGA and I am desperate and in an urgent need for a solution.
Thanks,
Yuval
12-16-2009 07:32 AM
And I need a moving Standard dev not windowed
THanks,
Yuval
12-16-2009 08:11 AM
12-16-2009 08:13 AM
yuval_yohai wrote:And I need a moving Standard dev not windowed
THanks,
Yuval
how fast is your data coming in, how many points to consider in calculation?
12-16-2009 08:22 AM
my data is 25Ks/sec
I need a moving standard dev (or variance) of a 1000 samples
I suppose a moving window of the last 1000 smaples.
Thanks,
Yuval
12-15-2019 07:14 AM
Hi, we are trying to implement a VHDL code for standard deviation and variance calculator. I saw that you have implemented it. Could you attach the zip file also. We have so many errors in our code and we do not know how to fix all of them.
12-15-2019 08:42 AM
Hello again, i see that you have implemented a standard deviaiton and variance vhdl code for the FPGA. If you still have it could you pleeeeaseeee send a zip file of it. We have a project and we have lots of errors that we are struggling for days.
I hope you see this !!!