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fpga Standard Deviation calculation - any examples?

 Hi All,

 

At last I had the time to check your solution.

 

It works fine while running on my computer yet when I compile it to the FPGA I get an error "FPGA Xflow Compile Error 2" and the output dialog says I should lower my resources or whatever.

 

I am using NI-cRIO-9072.

 

Any suggestion?

 

Thanks,

Yuval

 

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Message 11 of 20
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You might want to start another thread for the compile problem.  What version of Labview are you using? This might be a dumb question but you installed the FPGA Fixed Point Math Toolkit?  Maybe with Labview 2009 you don't need the toolkit.
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Message 12 of 20
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Another point to remember is that the provided solution is  a windowed solution as opposed to a moving solution.  what is your application requirement?  windowed or moving?
Stu
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Message 13 of 20
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strange, I had the feeling it is a moving Standerd dev. Are you sure?

 

Anyhow, I am still not able to compile the FPGA and I am desperate and in an urgent need for a solution.

 

Thanks,

Yuval

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Message 14 of 20
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And I need a moving Standard dev not windowed

 

THanks,

Yuval

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Message 15 of 20
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Just to be clear by what I mean.  I consider a moving or sliding function to produce a new result value for every data value representing the calculation over the last n points.  a windowed function produces a result value every n data (the window) points and "resets" itself.  The NI supplied RMS function is a windowed function for example.  A running function does not use n points, have a window or reset.  These terms are not universal so I wanted to clarify.
Stu
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Message 16 of 20
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yuval_yohai wrote:

And I need a moving Standard dev not windowed

 

THanks,

Yuval


how fast is your data coming in, how many points to consider in calculation?

Stu
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Message 17 of 20
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my data is 25Ks/sec

 

I need a moving standard dev (or variance) of a 1000 samples

 

I suppose a moving window of the last 1000 smaples.

 

Thanks,

Yuval 

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Message 18 of 20
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Hi, we are trying to implement a VHDL code for standard deviation and variance calculator. I saw that you have implemented it. Could you attach the zip file also. We have so many errors in our code and we do not know how to fix all of them.

 

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Message 19 of 20
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Hello again, i see that you have implemented a standard deviaiton and variance vhdl code for the FPGA. If you still have it could you pleeeeaseeee send a zip file of it. We have a project and we have lots of errors that we are struggling for days.

I hope you see this !!!

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Message 20 of 20
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