timed loop too long

[v1212800]

Hi,

how can I get a digital signal shorter than 25 microseconds? I am using a RT-system, and I am using a timed loop with the internal clock, but I can't get it faster than 25 microsecs.

Thanks
Tim

[v1212800]

I have read adittionally, that the timed loop has an overhead of several microseconds. Is there ANY way, to get digital signals with a duration of 1 microseconds, also for more channels? The best would be, if anyone could send me a sample VI to get any idea how I could manage that.

Thanks in advance

Tim

[preston_johnson]

Have you considered an FPGA plug in board for the high speed digital.  These time loops are very fast, and there is signal conditioning for up to 10Mhz inputs with the cRIO modules.  You can also do control on the FPGA board with LabVIEW FPGA.

an idea,