when RT controller programming runs gives -50400 error

[Pratima]

hi,

I am using cRIO-9104 with 9004 controller.I am using 9233 and 9237 module.I  am using a DMA fifo which depth is 1023 with my 9 channels(4 channels for 9233,4 channels for 9237 and one for time stamp).I am writing elements using build array with for loop in DMA.I am logging data in RT contrller by using DMA fifo (RT side) which depth is just twice of FPGA fifo.now i m facing -50400 error?is it error due to timeout,i tried to give all possible values (100,200,0,..............up to5000).please solve this problem.

pratima

[Van_L]

Hi Pratima,

Error -50400 says: The transfer did not complete within the timeout period or within the specified number of retries.

Essentially, your program timed out, the question is where?
Did this happen on the RT side? or the FPGA side?
If it happened on the RT side, this means FIFO underflow: RT tried many times to read the FIFO but there's not enough inside
If it happened on the FPGA side, this meas FIFO overflow. FPGA tried many times to write to it, but it's full.

You can try to set the timeout constant to -1, this allows it to wait indefinitely.

I would highly recommend you to follow the example code in the shipping examples of LabVIEW called: DMA Buffered Acquisition - cRIO.lvproj

Please give that a try

Van L
NI Applications Engineer

[Tarun_teotia]

hi Van,

         Thanks,i changed timed out with -1 at RT side.I have seen that shipping example also.I understood DMA concept.Now i have also facing a problem.i think first i should clear my application.i want to acquire data up to 50Khz from one NI-9233(4 channels),NI-9237(4 channels) and one timestamp(i.e total 9 channels).i am writing data in FIFO which depth is 32767.I am reading data at RT side where i m reading data in FIFO which depth is greater than 32767.now my queries are:

1.I am able to achieve data at 30KHz but not able to greater than 30Khz.

2.I am getting data in RT more than expected data.i calculated expected data=(total iteration in fpga * total channels(9))and total data which was read in RT.

I think my query would be clear.i stuck here i am trying alot to vary RT fifo depth.

Pratima

[The Specialist]

Hi Pratima,

The DMA fifo size for an FPGA and the RT side do not always have to be equal.  Typicall the FPGA FIFO side is VERY fast compared to the RT FIFO.  In general, I make my DMA about 4 x (# of channels) x (the number of samples I want per rt DMA read) .  My FPGA FIFO is almost always 1023, and in really fast applications 2047..

Then I read the samples out faster than what I collect them, but in larger chuncks.  In other words, if I want to read 8 channels at 1 kHz, then I will read 8000 samples each second, and have a FIFO of 32000.  If the data cannot wait every second to be processed I will read 4000 samples every half second and have a FIFO of 16000.  But keep in mind that the smaller the data chunk you bring in the more CPU your RT controller will have. 

The reason I have extra FIFO is if another parallel process needs some CPU, the data will go in the excess FIFO.  Then all you need to do is play some catchup to pull the data back out.

Also, always make sure that you setup all the settings (RT DMA size, data rate, etc.) before you actually start reading data.  That is very important. 

Anything else you think she should look out for Van?

[techbreak]

hi specialist,

                       I have used fpga fifo size smaller than RT fifo size.Still i m not able to achieve data greater than 25Khz.I have set 50khz in my hardware(NI-9233 and NI-9237).I notice one point that  my fpga while loop gets delay.Eventhough i used on SCTL in my for loop where i m  writing data in FIFO one by one from an array.what can be happen i have used Top level timing source in my TCL.solve this problem so that i can achieve the data at any rate without any loss.

Pratima

[The Specialist]

Hi Pratima,

Do you really have 3 different forum names 🙂  ?  I think what you are trying to say is that you get a delay in your Time Critical Loop reading the data off the DMA, since SCTLs cannot cannot have a delay (since it is true hardware).  Typically a delay in the time critical loop is a bad thing.  That means that you are either, you are causing priority inversion (bad) or you are running the CPU at 100% (bad).  I would suggest that you post your project so that we can all look at it and make some suggestions.  Not a true rewrite, but at least some helpful tips.

Also a trick that I have noticed if you think your DMA FIFO is falling behind reading on the RT side is to read zero elements out of the FIFO and then use the elements left output to immediatly read from the FIFO again the appropriate amount.

[techbreak]

hi specialist,

               actually i am using first time this forum support thats why i m not much familiar about its procedure,now its ok.I am sending my project.also sending a snapshot of  front panel of my RT-program.I again tried to achieve data again @50 khz.but i m not getting more than @25khz.i also run my RT program in simulation mode,i am getting data rate 1.2Mhz,after some iteration its stop due to full of fifo.please try to understand my code if there is some thing wrong tell me.

pratima

[Pratima]

hi specialist,

                 Sorry i didnt attach my project.today itself i will send it.

pratima

[Pratima]

hi ,

           I have attached my project in this forum.

[techbreak]

hi ,

          I have achieved data @ 50khz with using NI-9237 single module.If i am using NI-9233 and NI-9237 module together then its not achieving data @50khz.for 30-45 FPGA iteration it gives 50 khz,after this data rate goes down and again it regain with 50khz.this is cyclic process.exactly i want to know :can i not use both module simultaneously for 50khz SR?if in future i add more 9237 module (channels) then is it possible to achieve same data rate.I think my query is clear.if this is not please look at my code.which i have sent in earlier forum.

Pratima