Help to choose USRP module and develop custom algorithms

[ashish_86]

Hi,

We have a requirement for an SDR board, and here is our requirement:

1. We would want to sample a 70MHz signal and bring it down to Baseband frequency of 5MHz.
2. We would want to use our custom signal processing algorithms running on FPGA accessing eaw I-Q data.
3. The output of signal processing algorithm needs to be communicated to PC over TCP/IP for further processing.

Can you please suggest us a suitable combination of Mother and Daughter boards for the above application.

Assuming we find a suitable board from ettus following are the Questions we have 

1. Can we add our custom signal processing chain?
2. If we can add the custom signal processing, how do we get access to the raw base band I-Q signals?
3. Can we use standard development tools like Xilinx ISE/XPS/SDK for development of algorithms and programming the FPGA?. 
4. Is there a provision to program FPGA using standard JTAG, If not what are alternate ways ?

Thanks

Regards

Ashish Sharma

[cade]

Hello,

Unfortunately, there is no way to flush the USRP buffer in PC Memory.

This means that you will need to perform finite acquisitions to ensure that you are only reading all the samples in the buffer. The USRP Intitiate VI does not affect the configuration settings of the device. Because of this, you can call the initiate VI within the Fetch while loop (make sure you have finite sampling enabled) and fetch all the samples in the buffer by supplying -1 as the input for samples per fetch. This will not affect the configuration parameters that have already been defined in the session. When doing this you can elect to leave out the USRP Abort VI after the fetch is complete (within while loop). This should still maintain your ability to change the active antennas on the fly. 

The downside to all this is that your acquisition will be software timed which means that there may be some jitter in frequency of the while loop.

Please let me know if this helps. Thanks! 

[cochenob]

Hi Cameron-

I seem to remember having issues with trying to re-Initiate within a loop....but I wasn't reading all of the samples in the buffer with the -1 input...so maybe that was my issue.

I'll give it another try.  Thanks!

---

Brandon

[cade]

Hello Ashish,

As this forum only applies to NI's USPR devices, which already come pre-configured with specifc mother and daughter boards, you will need to direct your questions to Ettus Research.

http://www.ettus.com/home

Hopefully, they will be able to help you with intergrating your FPGA processor with the correct boards

[Sarah_Y]

Hi Ashish,

I'm not sure what happened to this thread and why comments from a different thread are showing up here.  I will try to do my best to answer some of your questions.

1. As far as a daughterboard, the WBX sounds like it will be the best board for your application.  It has a frequency range of 50 MHz to 2.2 GHz.

2. How large of an FPGA do you need?  The N series devices have some room on the FPGA to do some signal processing, but it is very limited.  We just released a new series of products, the X300 and X310 that have a Kintex 7 on them and would allow you to do a lot of signal processing on the FPGA.

3. Both the N2xx and X3xx motherboards are Ethernet based products.  The N2xx requires 1 GigE.  The X3xx has 2 10 GigE ports on it.  You can use an SFP+ adapter to communicate over 1 GigE if your system does not have 10 GigE.

For you next set of questions:

1. Yes, you can add your own customer signal processing chain.  Doing this with the X3x0 is a much better option than the N2xx due to the small size of the N2xx FPGA.

2. The UHD driver returns the raw baseband IQ signals.  UHD does do some processing to the IQ data.  For example, there is some DC offset correction applied.  I am not sure exactly what you need when you say that you want the raw IQ data.

3. Yes.  You can use Xilinx tools.

4. Yes.  The N2xx has a JTAG connector on the motherboard.  The X3xx has an exciting new feature--a USB JTAG port.  You no longer need a special Xilinx programmer to use JTAG, you can just use a USB cable.

My overall recommendation is that you check out the X300 and X310 motherboards and the WBX daughterboard.  We have 2 different versions of the WBX that work with the X3xx motherboards, one with 40 MHz of bandwidth and another with 120 MHz bandwidth.  I'm not sure which one will work best for your application, but both are supported on the X3xx.

Please let me know if you have any further questions and feel free to share more about your application.  The more I know about your project goals the better I will be able to help.

[ashish_86]

Hi Sarah ,

Thanks for giving good reply and suggestions. i will go with your suggestion.

i will let you know if i got another query.

if posible can i get your personal email so that i will easily communicate with your furthur.

With Regards

Ashish Sharma

[Sarah_Y]

I will private message you my contact info.  Also feel free to contact our sales team: http://ettus.com/contact  There is an option for pre-sales technical questions which will get your questions routed to the correct people.

[cochenob]

Cameron-

I gave your suggestion a try...but was unsuccesful.  I've attached some code below.  Maybe there's some subtlety in how you set in up...but the Fetch VI doesn't seem to like taking a -1 input.  In fact...I think the reason that I never tried that before was that because it's not mentioned anywhere in the documentation that an input of -1 reads all samples from the buffer (like it does, perhaps, with DAQmx or something like that).  In any case...I get an, "Unable to allocate memory" out of the Fetch VI if I wire -1 to the input.

Are you sure this is a valid input? 

I have configured things for finite input...and have tried defining or not defining an actual amount of samples to read. (Right now the # of samples is not wired, but I get the same result either way).

Here's a question....if I set up a finite acquisition of 10000 samples....and I get to the Fetch VI and there aren't 10,000 samples in the buffer yet....does it wait?  What if there are 15,000 samples?  Will it throw those extra 5,000 samples away if I re-initiate the device?

[cochenob]

Follow up.....the driver definitely doesn't seem to support the -1 input...but as long as you set up a finite acquisition and wire in a positive whole number, you can in fact re-initiate acquisitions within a loop (provided you don't call the Abort, as you mentioned).

I've tested this in a MIMO configuration and verified that there is no LO re-tuning.  The measured phase between the two radios stays constant regardless of how many initiations you do, or how many times you switch antennas.  The only downside is that you must set the system clock back to zero and wait for how much ever time you've set to wait to begin acquisition each time you want to change antennas.  Probably a reasonable price to pay.  (Of course, if you're not doing MIMO, or don't care about time synchronization, then you don't have to worry about this anyway).

Thanks for the suggestions.

---

BC

[cade]

Hello,

I'm glad that you were able to find an acceptable solution.

As long as you know how many samples you collect per finite acquisition, you can simply fetch the same amount of samples using the USRP Fetch function. However, it is still strange that the -1 on the samples to fetch input still gives you issues. It is possible that this input may not be allowed, but based on the error you were getting, it seems more like an error related to LabVIEW running out of memory when trying to fetch several samples at once from the PC buffer. I will try to verify this when I get a chance.