Download Bitfile to Flash on FPGA in VeriStand

[B2.718]

Hi,

I was wondering how to download an FPGA bitfile to flash memory on an FPGA using VeriStand. I am using a PXI chassis and a PXI R-series FPGA.

I am hoping that the answer is

1) Setup the FPGA VI to run when loaded on FPGA

2) Open the VeriStand System Explorer, set the System Initialization to Run System Definition on reboot.

3) Deploy.

Or is the bitfile stored on the chassis hard drive and then imported onto the FPGA each time the chassis is booted? 

If I undeploy the system definition file I assume the flash on the FPGA is cleared, is this true?

Thanks,

Brent

[Zach-H]

Hey Brent, 

I'm not sure of the exact implementation off of the top of my head, but I believe VeriStand uses an Open FPGA Reference similar to other Real-Time executables. I don't think that it has the ability to embed the Bitfile to the Flash memory of the FPGA. Alternatively, you can do so with the LabVIEW FPGA Module, with the RIO Device Setup Utility to do so, which is discussed here, or you could try turning these VI's into a workspace tool. 

All of the Bitfiles following the standard FPGA personality template (discussed here) should wait on VeriStand to start running the system definition before they begin to execute their communication loop as the timing engine will need to wait for a start trigger. Parallel processing loops would begin immediately though. 

As for clearing the FPGA, I would assume the default functionality of the Close FPGA Reference, resetting the FPGA as the system is undeployed.

I'll talk to some colleagues in R&D tomorrow and see if I can confirm the above for you. 

What is it that you're looking to accomplish/avoid by embedding your Bitfile into the FPGA Flash? Are you worried about the FPGA being in an indeterminate state?

Cheers,

Zach 

[B2.718]

Hi Zach,

I would like my FPGA to be configured from the flash memory so that it is operational the moment it gets power. I don't want to rely/wait on VeriStand to load the bitfile each time before the FPGA is ready to go.

To clarify, are you suggesting that if load the bitfile to the flash using RIO Device Set-up utility in LabView the parallel loops would start immediately, but the communication loop would begin after VeriStand triggers them? This would work ok if this is the solution. I see a potential issue of VeriStand trying to re-load the bitfile to the FPGA if the bitfile is in the system definition.

I have had an issue with connecting LabView to the chassis. It seems that LabView RT overides VeriStand and the chassis no longer opens VeriStand automatically after LabView accesses it. Each time this happens I reinstall VeriStand and it works again. See known issue 149703 . I would prefer because of this nuance to use VeriStand directly.

Thanks,

Brent

[Zach-H]

If VeriStand uses the FPGA Open Reference (still in the process of confirming), it will check to see if the Bitfile currently deployed on the FPGA is the same as the one its trying to open a reference to. It will only overwrite the Bitfile if it was expecting a different Bitfile than it finds on the FPGA.

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To clarify, are you suggesting that if load the bitfile to the flash using RIO Device Set-up utility in LabVIEW the parallel loops would start immediately, but the communication loop would begin after VeriStand triggers them? This would work ok if this is the solution.  

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Yes, that's what I'm suggesting. You could also use the FPGA replication VI's as a Workspace tool. 

As for 149703, the problem is that the startup tokens in the lv-rt.ini file change to their defaults rather than pointing to VeriStand. (The INI file is read only at boot) The two tokens are discussed in this KnowledgeBase article. If you copy those tokens from the lv-rt.ini file of your target when VeriStand is running normally (they should have a different file path than just startup.exe) you can manually correct the INI file rather than reinstall VeriStand. Re-installing VeriStand just changes the tokens for you automatically.  

[B2.718]

Hey Zach,

Were you able to confirm if VeriStand uses the Open FPGA reference? Does VeriStand overwrite the bitfile if it is already running?

Thanks for explaining how to fix the INI file, I figured it was a pointer somewhere.

Brent

[Zach-H · Accepted solution]

Hi Brent, 

I heard back from R&D today. VeriStand does use the Open FPGA VI Reference, meaning the bitfile will not be overridden if it detects the correct bitfile already running. 

"By default for some FPGA targets, this function opens and runs the compiled FPGA VI on the FPGA target if the FPGA VI is not already running.) - Help FPGA Open VI Reference.

When the system definition is undeployed the FPGA is reset which  is the default behavior of the Close FPGA VI Reference.

"Closes the reference to the FPGA VI and resets the VI if no other references to the VI are open. Resetting the VI returns VI controls and indicators to default states, sets global variables and uninitialized shift registers to default values, and clears FIFOs." - Help FPGA Close VI Reference. 

Zach

[B2.718]

Thanks for your help!