Excessive cross-talk when using external counter timebase

[Axiom]

Hi all,

Hardware: PCI 6602

Software: DAQmx 7.4, Ansi C

I have observed and excessive amount (about 400 or 500 mV pk-pk) of cross-talk when using an external counter source for pulse generation tasks.  The hardware setup is: external TTL source (1MHz to 10MHz rate) connected to CTR0 SRC, generated pulse observed on CTR0 OUT.  The source is a very clean square wave coming from a pulse generator with 50 Ohm output impedance.  According to the 6602 user manual, no cross-talk should be observed when the source output impedance is less than 100 Ohm.  But, a fairly large (400 or 500 mV pk-pk) component of the source signal is clearly present in the output signal -  it is definetly cross-talk and not noise because by zooming in on the scope you can see the source frequency clearly.  So far, I've tried keeping the CTR0 SRC and CTR0 OUT grounds (pin36 and pin39 on connector block) separate and also connecting them together - this does not seem to make any difference.

Can anyone tell me how to clear up or at least reduce this problem?  BTW - I'm using the SH68-68-D1 68-pin 2 meter shielded SCSI cable (part number 183432-02) and the CB-68LPR unshielded screw terninal block (part number 777145-02) to interface to the board.

Thanks,

Jeff

[Tom_W_[DE]]

Hi Jeff-

I am also seeing noise around the ground level when measuring with my OSC.  However, the noise is well within the TTL specification of 0.4V relative to ground for VOH.  The ringing I am seeing (and I suspect you are seeing) is occuring around 0V, so the signal may be 0.4Vpp but should only be exceeding the 0V system level by approximately 1/2 of that.  So, while the noise is definitely present, it seems that the card is still operating well within the specified limits.

Hopefully this helps-

[Axiom]

Hi Tom,

Thanks for your reply.  The ringing (noise if you like, but it is definetly being coupled to the output signal from the source) is occuring during both the logic low and logic high periods of the output.  I agree, this is still within the TTL noise margins, but is staying within the margins the only important thing? - e.g. what happens multiple devices are clocked using the same output pulse - the pulse shape is degraded slightly due to cabling and input capacitance etc, and now, because of the additional ringing, the logic thresholds are being crossed when they shouldn't be.  If you consider that the source signal is 5Vpp and the induced ringing is 0.4Vpp then the rejection ratio would be 20*log10(0.4/5) = -22dB, not very good.  The situation is not as bad when one of the internal timebases is used as the source but this particular application requires an external one.  So, I'm looking for ways to reduce the ringing if you're aware of any.  One possibility might be to reduce the cable length - I'm using the 2m cable so maybe you could try the 1m cable for me and see if things improve.

Jeff

[Tom_W_[DE]]

Hi Jeff-

I definitely understand your concern.  I tested yesterday with both 1m and 2m cables and did see slightly better results with the 1m cable.  I wouldn't call it a significant change (on the order of 10's of mVpp), but it did make a difference. This may be an option worth trying for you. 

However, I would still like to suggest that a 400mVpp signal corresponds only to a 200mV overshoot of 0V.  This may indicate a less than stellar rejection ratio in theory, but in terms of TTL-compatible external hardware you should be well within the limits of operation.  The best suggestion is to use the internal timebases, but if this is not an option then you should be very conscious of proper termination and compensation with the loads you are driving.  Perhaps a small parallel capacitor would be helpful in suppressing some ringing at the output.

Hopefully this helps-

[AnalogKid2DigitalMan]

Would an isolated buffer/driver or Schmitt trigger on the ouput clean up the signal appreciably? Just a thought