Re : PXI 6552 : generating two synchronized clock signals

[rinkevoli]

I'm using the PXI 6552 card.

I want to generate two digital clock signals at the same frequency.
The second signal is synchronized with the first one but delayed.

How can I generate theses two signals with the PXI 6552  and export them to two different outputs ?

Fon information, I use Labwindows/CVI.

Thanks in advance

Rinkevoli

[Benjamin_M]

Hello,

The PXI-6552 devices support data delay; which is phase shifting of digital signal relative to the clock. For example, each generation channel can be independently configure to generate with the rising edge of the sample clock, the falling edge of the sample clock, or some delay from the rising edge of the sample clock. However, all the genration channel that are configured for delay must share the same delay (it is ok for you because you have only two signal to generate).

You'll find examples of this in the directory : \Program Files\National Instruments\CVI80\samples\niHSDIO\Dynamic Generation\DynamicGenerationWithDataDelay.

I hope I answer the question,

Regards,

Benjamin M
NIF

[rinkevoli]

If my understanding is good, in the example, all the assigned generation channels  are delayed .

In my application, I want to generate two signals and delay only one. How can I delay only one generation channel ?

[Onome]

Specify the channel(s) you intend to delay in the "channel list" parameter in the niHSDIO_ConfigureDataPosition function.  The "channel list" parameter to the niHSDIO_ConfigureDataPosition function must be a subset of the channels configured in the niHSDIO_AssignDynamicChannels function (does not have to be the exact same channels as in the example).