Enhanced Alias Rejection and Synchronization

[crimolvic]

Hello,

I am working on the synchronization between DSA devices. In this case a 4461 and a 4472b.

Here is the thing. Each device has a ADC Filter Delay which is dependant from the sampling rate. Refer to tables on page 5 of the Specifications for the 447X, and on page 6 of the Specifications for the 446X.

As you can see, in both tables there is no common delay between the two boards. For example: If EnhancedAliasRejection is set to TRUE and if the sampling is 20 kS/s, the Filter delay for the 4472b would be of 35,35 samples and for the 4461 of 47,5. In other words, the measurements will be not in phase.

If the EnhancedAliasRejection is set to FALSE, the delay is for the 4472b of 38,7 samples and for the 4461 of 63 samples. Once again there is a misphase between the measurements.

am I right with this?

How can I be sure that there is no (or near no) misphase between my measurements? I can think in two options:
1. Correcting the phase difference by software in a post-procesing stage.
2. Inducing a delay on the start of both devices causing the sum of the filter delay + induced delay on each device to be equal.

What do you do in order to have simultaneous acquisition between 446X and 447X devices?

thank you,
cjmv

[Elmar_NI]

Hello CJMV,

its not possible to syncronize both devices with a different sample rates.

http://digital.ni.com/public.nsf/websearch/83C82B37411D837286257221006D5288?OpenDocument

Use the link more information about syncronize both devices with the same sample rate.

http://digital.ni.com/public.nsf/websearch/A133ED27DF9BCC5986256F2E004BA342?OpenDocument

Kind regards,

Elmar

[crimolvic]

But I am not talking about different samplig rates for the two devices. In the examples that I gave in the first post, the filter delays are for a sampling rate of 20kS/s in both devices.

The sampling rate is the same for both devices, the misphase come from the different amount of filter delay that the two devices introduce. In both cases: when EnhancedAliasRejection is set to TRUE or to FALSE, the amount of filter delays for both devices is different (once again, the sampling rate is the same)

[crimolvic]

Elmar,

regarding using a different sampling rate for both devices (is not that I am intended to do that), I found on NI DSA Help, under:

NI DSA Help > DSA Device Concepts > Synchronization > PXI DSA Heterogeneous Synchronization

the following text (third point)

When you synchronize boards that have different sample rates, the rates on any two devices in the system must be a power of two. For example, if the master device is sampling at 100 kS/s, the slave devices can run at 200 kS/s or 50 kS/s, but not 40 kS/s.

So, it is not clear to me if I can or can´t use different sampling rates in both devices.

Best regards,
CJMV

Message Edited by crimolvic on 05-03-2007 04:42 AM

[Elmar_NI]

Hello CVJM,

phase offset can be issue with DSA synchronization, but you seem to have found two possible solutions to the problem.  The second approach that you mentioned (adding delay before the start of the lower-delayed device’s acquisition) is less feasible than the first approach.  First, you’ll need to create two separate AI tasks, thereby adding complexity to the code.  Secondly, the differences between the filter delays may not be an even multiple of the sample clock period, so even after adding the delay, you may still have a slight phase mismatch.

On the other hand, if you use the channel expansion method for the DSA devices (adding both device’s channels to the same task), they will be synchronized, but with the phase offset as you mentioned in your post.  The best way to account for this offset is to use the software postprocessing to remove the extra samples of the lower-delayed device. 

Kind regards,

Elmar

[Jeff_T.]

Hello CJMV,

Anytime you try and synchronize two devices that have two different Delta Sigma Converters (like the 4461 and the 4472) we have to work with this significant but deterministic phase delay.  There are ways to compensate for this delay in software but these strategies all revolve around:

1.) Are you using multiple tasks or 1 DAQmx Channel Expansion task for all your DSA devices?
2.) Are you performing finite or continuous acquisition?

If you are performing finite acquisition, then compensating for the delay is quite easy.  The 4472 data is about 24.3 samples ahead of the 4461 so you can delete 24 samples from the beginning of the 4461 data and 24 samples from the end of the 4472 data.  If you need even tighter synchronization, you can compensate for the non-integer sample delay with some interpolation.

If you are performing continuous acquisition with multiple tasks then you probably have a read function inside of a software loop.  You can use the first iteration of the read loop to read 63 samples off the 4461 buffer and 39 samples off the 4472 buffer.  You can discard that data and then start reading your block size (i.e. 2048 samples) from both tasks on each remaining iteration.  Compensating for the non-integer sample delay is much more difficult in this instance but experiments have shown that there is only about 24.05 samples of relative delay between the two devices.  The delay in the spec sheet is digital delay only, there is a little more delay added from the analog circuitry and FPGA on the device.  Your devices won't have exactly 24.05 samples of relative delay but the point is that the non-integer sample delay may be small enough for your application.

If you need to perform a continuous acquisition using channel expansion (all devices in one task) then the compensation is much more difficult.  I have a VI that was constructed using the LabVIEW Digital Filter Design Toolkit that can be used to delay your 4472 samples by 24.05 samples.  Both your devices will then have data with an equal delay of 63 samples which can be discarded.  If you need access to this VI let me know and I can give it to you.

Best Regards,

Jeff Tipps
Product Support Engineer: DSA
National Instruments