LabVIEW FPGA Idea Exchange

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Fixed point constants like to show you a lot of precision more often than not.  It would be nice to be able to right-click a number and instantly select hide trailing zeros.

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I know its not necessarily a LVFPGA issue, but its us LVFPGA users that use fixed point numbers most often.  Why don't fixed point numbers always show coercion dots.  If every unnecessary numerical digit wastes chip resources, then isn't it more important that we know about these coercions so that we can avoid them?

 

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I have to remember to place a comment next to every memory element so that I can quickly know its size.  This is especially important because I can't get to the property window if I'm viewing the vi outside of the FPGA Target Scope. I can view the data type of a memory/FIFO element by hovering over the wire that goes into a read/write property with the context help window open, so I don't really care about that.  However I cannot view its size.  This could be fixed in one of two ways, add it to the context help when you hover over the element or display it directly on the memory element.

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The Tick Count function in LabVIEW FPGA can represent time periods with tick count accuracy of up to 2^32 clock cycles, that is (using the standard 40 MHz FPGA clock) about 107 seconds.

Sometimes I need to handle longer time spans, and I use this example.

 

I suggest to implement a built-in 64-bit tick counter.

 

 

 

64bittick.png

I am looking for a way to transmit 9 bit Address array  17 bit Data Array in a Manchester Format. I am using a PCI-7813R  with SCB-68 Interface. I have breadboarded the push pull circuit to generate the +/-5V Signal. 

 

 

NI has to link to Manchester enable encoding.

http://zone.ni.com/devzone/cda/epd/p/id/6400

 

http://decibel.ni.com/content/docs/DOC-2824

 

2nd link mentioned about half bytes and update output state that I do not have an understanding of.

 

The Problem is since Labview does not work like a Hardware Clock. The Clock in my program does not transition a full period during the iteration. Thus the output is wrong.   I have tried Global variables without any success.

 

I am trying to duplicate the DOC-2824 picture of Manchester Enable Communication.

 

 

My Code  is attached.

 

 

 

Any assistance would be appreciated.


Greg

 

 

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I have several FPGA projects that require significant compile time (up to 1.5 hours), and for that I am thankful to have my compile server running on a separate computer.

 

The issue comes with the seven Pre-Compile steps that occurs before LabVIEW sends to the code to the compiler. On one particular project this action alone can take up to 35 minutes during which time I can do nothing on that machine.

 

I would like to see much of this precompile time moved from the development environment to the compile server. There already exists a mechanism for updating the user with the compile status so those precompile errors could be annunciated in a similar fashion.

 

Get the development system back online as quickly as possible.

I have several projects that use the same code modules.  FIFOs are used to communicate with these modules.  It would be really nice if I didn't have to keep recreating the same FIFOs for each new project just to be able to reuse my modules.  I suggest being able to save FIFOs (DMAs also) in a lvlib file, similar to project variables in the Windows LabVIEW.
We can programmatically mass compile VI's and build executables but there is no easy method to compiling FPGA code.  We have a large application that consists of C++ and LabVIEW code.  We have automated our build process but we still have to compile the FPGA code using a procedure.  It would be nice to write a script or a VI that would compile all of our FGPA code.

Writeable inputs to FPGA I/O nodes can be left disconnected without any warning (or broken VI indication) from the VI in which the I/O node is used. This can cause some vigorous head-scratching if the missing connection is not immediately obvious as in the screen shot below. For obvious reasons, FPGA controls have no connector assignment or "Recommended, Required, Optional" attribute. In that case, and to avoid playing "Where's Waldo" on the block diagram, I suggest making FPGA I/O node input connections implictly "required", and if not, the VI would be broken. This would be the same behaviour as seen with cluster nodes. 

FPGANode.png

The Control / Indicator pull down menu gets unwieldy with a lot of Controls on the FPGA Front Panel. 

 

I would like to be able to sort the names alphabetically so they are easier to pick in the pull down list.

With multiple hosts in one project remove the restriction of FPGA target names.  If I have 2 cRIOs in one project and the FPGA in those cRIO's is the same then so should the FPGA target name.

 

FpgaName.jpg

 

 

Of course, FPGA target names must be unique if they are within the same host.

The NI 9802 (Secure Digital Removable Storage Module for CompactRIO) is a cRIO module that has two SD memory card slots. The problem is that the programmer cannot index the ports as "0" and "1". The solution is to write a code for "0" and repeat it for "1".

 

The proposal is to allow the user to select memory card by a terminal in the "Method" and "Property" nodes.

 

Since the maximum amount of memory per card is 2 GB, if more than 2 GB is needed, the programmer should manage to split the data in two cards. Right now the code should be duplicated and selected by a "Case" structure. In many other situations the programmer may need to use one or other card, like when a big file should be saved after the usual check of the available free space in both cards.

 

 

Please give Labview FPGA the ability to program any FPGA.
I would like a way to name all of the connector I/O from an external souce - perhaps an excel file.  I envision importing a single file for all of the I/O.

Even though ibberger touched the concept in the idea , I do think that most o people uses LabVIEW under Windows environment. Compiling a FPGA VI happens all in the PC under Windows. I noticed that during this process the compiler uses only one core. Since I'm using a machine with a 4 core processor, the CPU use rarely goes above 25%.

 

My idea is to update the compiler allowing it to be multicore. The user should have the option to limit the maximum number of cores available to the compiler. This is necessary because the user may want to continue working, while the compiling process is being done in background.

I'd like to have a dedicated FPGA Compile Server, based on a realy slim OS, e.g. damn small linux oder even PharLab? The OS does not realy matter, as far as it is multi-core capable and it should use as little system resources as possible, to get as much ressources as possible for the compilation process.

 

Purpose: get max. compilation speed

 

It would be nice to have "time unit converters" in the Labview FPGA Timing menu.

 

My need would be, to automatically, convert Ticks to µs, according to the local Clock cycle frequency ...

 

  • Ticks -> µs
  • µs -> Ticks
  • Ticks -> mSec
  • mSec -> Ticks

 

Using this kind of automatic converters in place of "manual calculations with constants" would help during code evolution ...

The actual "Wait on ... I/O method" has an input named Timeout ... With no unit !

 

Wait on I_O.PNG

 

So i went on the NI forum and i found this article ... http://digital.ni.com/public.nsf/allkb/0D8325309894115286256F3B00341159

 

It would be nice to add the unit in the name of the input parameter like Timeout(ticks)

 

Better idea ... it would be nice to be abble to configure the timout unit like timing objects like this ...

 

Wait on I_O_2.PNG

 

 

Like a Formula node or a math script node why not a RT node that will support Verilog and VHDL? Yeah yeah i know the time taken to code will take a hell a lot of time compared to what can be sweetly done in lv (So dont compare) but at times verilog support will have its advantage.

The first thing you hear about programming FPGAs with LabVIEW is: use single-cycle loops. But if you build a state machine (while-loop + enum + case structure), in many cases you cannot make the outer while loop in a single cycle-loop, because not every state fits into a single-cycle loop. Therefore you have to place the single cycle-loop into every case, which has to run in one cycle, which takes up block diagramm space and is cumbersome. Therefore my idea to create a single-cycle case structure: it uses the same compiling mechanism of the single-cycle loop on every case, which is capable of running inside a single cycle. It would be nice, if this behaviour is configurable, meaning I can decide from case to case, if it is a single-cycle case or not. Some kind of right-click menu options like these: "make this case single-cycle", "make every possible case single-cycle", etc. Of course the mode of the case (single-cycle or not) should somehow be displayed.

 

Regards,

Marc