Compilation FPGA

[maybebis]

Hello everyone,

Do you know what 'MET' means at the end of the FPGA compilation (final timing)?

Thank you 🙂

Christophe.

[Intaris · Accepted solution]

It means it was successful in reaching the timings required.

i.e. "meeting" the required specification

[maybebis]

So much the better :))

Thanks you.!!