Internal software error in the LV2016 FPGA Module (Error -61499)

[Crowbar]

Hello!

Just moved from 2014 to 2016 my FPGA projects and faced an error:

Error -61499 occurred at niFpgaCompileWorker_AnalyzeTimingPaths.vi<-niFpgaCompileWorker_CheckForErrors.vi<-niFpgaCompileWorker_JobComplete.vi<-niFpgaCompile_Worker.vi:6460001

Additional Information: TimingReportFileNotFound: exception type "NI.LV.FPGA.Xilinx.TwxParseFileNotFoundException".

Details:

• Project was saved to 2016 and rebuilt with no additional changes
• This error occurred on different machines
• Target is cRIO 9063
• Xilinx Vivado 2015.4
• Project uses VHDL CLIP, if i remove it - error disappears
• Same project with VHDL CLIP compiles normally for cRIO 9075 (ISE)

How can i beat this error?

[DCarreon]

Hello Crowbar,

Here are some links with different troubleshooting options that i think might help you

http://digital.ni.com/public.nsf/allkb/5B8827503F7D90F386257BEA002D8E99?OpenDocument

http://digital.ni.com/public.nsf/allkb/0621DAF92B1731138625715E0075A702?OpenDocument

Regards.

[Crowbar]

These don't work. I've tried to reinstall all software components - the result is still the same.
Error arises on finalizing file step and is based on a report file missing.
My CLIP uses additional timing constraints and they worked normally in 2014 on the same target.

[Jeff_Giacone]

I am getting the exact same error, hopefully a fix will be found soon

[Crowbar]

What can I say for now:

1) I was able to fix this error by removing some timing constraints in my CLIP's xdc and part of vhdl code which worked in 2014

2) Definitely cRIO timing constraints and rules of there forming for the given chassis have changed a bit since 2014 release (clock groups and there relations) cause i see clear timing violations in compilation logs. But this errors weren't reported as timing fails during compliation - instead internal FPGA module error was thrown!