[Labview FPGA]: Use Xilinx memory bloc in HDL integration node

[mhed]

Hi

In my projet, i 'd developped my own VHDL module, and integrated it into my LV FPGA project with an Integration node.

But for an evolution of my code, i'm wondering if it is possible to use directly in my own VHDL code, some Xilinx library (as memory bloc).

Thanks.

[Louis.L]

Hi mhed,

With a CLIP (Component-Level Intellectual Property) node it should be possible.

Here some tutorial which should help you:

- Importing External IP Into LabVIEW FPGA: http://www.ni.com/tutorial/7444/en/

- Xilinx CORE Generator IP palette: http://www.ni.com/white-paper/12918/en/

Regards

[mhed]

Hi Louis,

Thank you for your answer.

However, it is not what i need.

I need to use Xilinx memories blocks (built-in blocks of the FPGA) inside my own VHDL code. So i'll use those memories not directly inside my LV FPGA project, but in my "external" HDL code.

[Dragis · Accepted solution]

You can use just about any Xilinx IP (or other IP for that matter) in your external code. For instance, if you generate a memory block using Block Memory Generator you can instantiate that IP in your own VHDL. 

[mhed]

Thank for your answer.

It will help me very much in my project.