NI cRIO-9082 and EtherCAT slave NI 9144

[Mauritius]

Hello all.

I have a project containing cRIO 9082 with a EtherCAT master connected to a NI 9144. 
Both system runs FPGA code. 

I build a startup Real-Time Application located in "c:\ni-rt\startup" and it contains startup.rtexe and startup.aliases, and a folder "data" with the file "FPGA9082.lvbitx".

Where is the fpga code for the 9144 stored? And how it it loaded into the EtherCAT slave NI 9144? 

Can i move/FTP the files to another setup of the cRIO 9082 and NI 9144, "[project location]\builds\Real-time application\c\ni-rt\startup\*" and it will load the code for the NI 9144?

Thanks.

[DirkW]

The ethercat driver brings an example that shows how to use the ethercat state machine on FPGA to wait for the ethercat bus to go Operational. If that happens the FPGA code on your 9144 will start running. The bitfile can be downloaded from project or programmatically via EtherCAT FoE Write. There is an example for that as well. You have to download the bitfile at least once so the project provider for LV can create the .foe file for your bitfile (same location as your bitfile). This file then can be downloaded programmatically. As said you do not need to do anything in LV RT to get the 9144 bitfile to run. It will run automatically when switched to OP via ethercat.

Hope that helps.

DirkW

[Mauritius]

Hello Again.

My project is structured as shown.

Using FPGA project for both chassis.

I use 2 ways to run / test code:

1st way using development computer:

* Modify and save changes to .VI-files.

* Rebuild fpga for NI9082 and NI9144. (approx 2 hours)

* right click > "Deploy all" on "RT CompactRIO".

* open "9082.vi" and run that.

* open HOST.vi and run that.

2nd way using "My Application" and "My Real-Time Application":

* Modify and save changes to .VI-files.

* Rebuild fpga for NI9082 and NI9144.

* right click > "Build" on "My Real-Time Application".

* right click > "Deploy" on "My Real-Time Application".

* reboot NI 9082 using power button.

* right click > "Build" on "My Application".

* Go to [project location]\builds\Host application\ and run *.exe file.

Problem is that when using the 2nd way, the system does not use the same FPGA code, as when runnig it the 1st way. Do i miss something? Does Deploy not deploy FPGA-code?

Is there not a way to compile files and transfer them easily to the system, so that the cRIO and slave (NI9082 and NI9144) can run automaticly after a reboot?

https://www.ni.com/docs/en-US/bundle/ni-9144-getting-started/page/gsg_purpose.html

and

http://www.ni.com/pdf/manuals/372084a.pdf 

does not provide much info, when trying to understand the build and deploy system.

A hint/link to manual would be nice. 🙂

[DirkW]

Yes, correct Deploy does not deploy the FPGA code. The difference between and FPGA Build Spec and an RT Build Spec is that the FPGA one creates a bitfile and the RT one creates an EXE file.

For your ECAT chassis you have to download the Build spec before executing the RT code. The good thing is there is not RT Host Interface API call for the ECAT bitfile. It just runs when it is going to opperational.

DirkW

[Mauritius]

So there is no easy way of deploying the FPGA files to the systems?

I need to switch into configuration mode, and manually chose to opload the LVBITX files every time i have a FPGA design change?

I dont think this is very rapid way of testing and deploying designs. 

It would be easy if there was a kind of "Build and deploy all files to targets and make it run at boot" option.. 🙂 

[DirkW]

Well that was the easy way. There are ways of deploying bitfiles to targets programmatically. Please refer to the help file in LV or to KBs on our webpage.

DirkW