crio multiple fpga vi

[MuratG]

Hi,

I have constructed two fpga vi's for cRIO FPGA and tried to run them parallel in a host vi but when I run the host vi then the fpga vi's did not work properly.

I attach the vi's. What is the problem with these codes?

[Prashanth]

Hi There,

Are you trying to run two different vis on the same FPGA target at the same time? What is your hardware target and what versions of software do you have? Have a great day!

Regards,
Prashanth 

[John Rich]

You should only have one FPGA program called from the host at any given time.  Set the programs up to run in parallel on the FPGA and connect to a single program from the host.

[MuratG]

Hi John,

For my project I planned to use 4 FPGA vi's running parallel, passing data through RT module (to control the input and outputs). Is this possible whatever the size of the fpga vi's are?

[JMota]

Hi engt,

I just want to re-affirm what John said, which is that you can only have one top-level FPGA VI loaded on the FPGA Target at any given time. In other words, you can't have multiple top-level FPGA VIs on the FPGA VI running in parallel, no matter what the size of the FPGA VIs is.

If what you need is to have parallel execution of FPGA code, you need to fit that into one single top-level FPGA VI (you can use subVIs if that makes sense for your app) and put every unit of prallel execution in its own loop (while loop, for loop, timed loop; flavor of the loop does not matter).

If you don't need parallel execution of your code and can't fit all your logic into a single FPGA VI, then you need to serialize the execution of your FPGA VIs.

I think the confussion lies in the fact that in regular LV or LV RT you can open references to multiple VIs in the same machine at the same time and interact with all of them from your program. In LV FPGA, the concept of multiple references to FPGA VIs on a given FPGA Target does not exist; there can only be one valid reference at a given time.

Hope this helps.

JMota
National Instruments

[MuratG]

Hi,

When I try to use your method then the fpga code did not work. With a small search I found that a sub vi -includes another sub vi- does not work. To eliminate this problem I took all the sub vi parts to up but now I have a question. The FPGA vi's that I described before (4 FGPA vi's) now works as a sub vi under top-level FGPA vi but the while loop wait times are different. One vi works with 20microsecond steps(50 kHz operation) the second one  with 200 kHZ  and the others with 200 MHz (or 100 MHz).

Is this code architecture is valid or do I have to change the operation frequencies of these four FPGA sub vi's.

Thanks

[JMota]

Engt,

The thing you need to be aware when using subVIs on FPGA is that only the controls and indicators of the top-level VI are accessible from the Host Interface VI. That's one of the things you need to be careful when defining your FPGA application VIs hierarchy. I guess that's the reason why that didn't work for you.

If I understand correctly what you describe as your architecture, that's perfectly fine. That's one of the nice things of LV FPGA: you can achieve true parallelism since all the code at the end gets translated into a digital circuit which can run multiple components simultaneously. In this case, each while loop will run at its own speed independent of the others (unless you create some dependencies between them, which is optional and depends on your app).

JMota
National Instruments

[P. Jack]

Hello All,

I was debugging my FPGA VIs for two days now and I just found out that running two or more VIs cannot run at the same time in a a sing RIO device. I am currently using 7811R.

I am dead!!!! My FPGA was just delivered and I have spent the last month coding my FPGA VIs (plural).

So the suggestion in this thread is to put all the VIs in a single top-level VI as subVIs. How about teh controls and indicators I used inside SCTL in the subVIs? If on my top level VI I changed the controls that feeds the terminals of the subVIs, in which those terminals are controls inside the SCTL, can I get a real time response? Do I need to use global variables? Is global variable possible in FPGA VIs?

I was hoping, wishing actually, that this thread is out-dated.

HELP PLEASE.

I'm on a schedule to deliver my project or my termination papers.

Best regards all,

P. Jack

[mrak1]

Hi,

Unfortunately for you, this thread is correct and you can only have 1 LabVIEW FPGA VI running at a time. 

However, here are some tips that may help you out:

• It is possible to load different FPGA personalities during run time.  Therefore, if you can separate your application into two different applications, you can load them on the FPGA while it is running ( only takes about 1 second to switch the FPGA to another personality)
• Instead of putting the multiple FPGA VIs into a top level VI, have you tried to copy the block diagram from one into the other?  In other words, combine them into a single VI with multiple parallel loops?
• If you are having trouble with space on the FPGA after combining the FPGA block diagrams into one there are many documents online that will help you optimize the FPGA VI.  For Example
• Combine boolean indicators into a single U32( will save a significant amount of space)
• Reduce the usage of arrays on your FPGA VI ( if you have them).  There are other methods of storing this data such as a FIFO or the memory on the FPGA
• Since you are using the digital only board and if memory serves me right, you can read the port instead of each boolean individually.  This would save you some diagram space as well as some FPGA space.
• Last but not least, consider contacting a systems integrator to assit with the development of your FPGA VI or the system as a whole.  I know of one that does great work with FPGA's: www.viengineering.com  . 

Mike

V I Engineering

[P. Jack]

For the last hours, I have been copying the block diagram of my subVIs to the block diagram of tht top-level VI. So far, I am not yet running out of resources. Though the maximum clock operation that I can work on degrades.

Another question, say I have multiple host VIs, can they perform simultaneous read and write to the FPGA VI?