fpga simulation, ModelSim warnings on DMA FIFO

[fbondoux]

Hello

I'm using LabVIEW 2010 with ModelSim SE 6.6e for my simulation exports. The hardware is a PCIe-7851R board.

When using a target to host DMA FIFO, I've noticed that ModelSim sometime prints this error message:

# ** Error: NiFpgaDualPortRam: An address was read while being written. This could cause the data output register to go metastable. The problem will be even worse if the data output register is not located near the block RAM.
# Time: 6825 ns Iteration: 3 Instance: /tb_nifpgasimulationmodel/nifpgasimulationmodel_instance/targettoplevelsim_instance/thewindowx/thevi/n_interface/miteinterfacex/dmablk/dmacomponents(0)/gennifpgachannel/mitedmacomponentx/geninput/dmainputx/nifpgamitereadinterfacex/blkaififo/blkfifo/nifpgafifox/nifpgadualportramx/geninferredram/inferredramx/verifysameaddressnotreadwhenwrittenblock

The occurrence and frequency of this message depends on the frequency of the FIFO write calls.

I haven't seen any transmission error but since it’s my first time using LabVIEW, I wonder if I’ve missed something or if it’s an inaccuracy in the simulation.

Attached is a minimal test case project with its VHDL testbench. The FPGA VI just writes one 32 bits integer every 16 clock cycles which is enough to make ModelSim regularly print the message.

Thanks for any pointer.

[Brice.inno]

Hi,

Thanks you for your post on National Instruments Forum's.

Do you use an example VI?

[fbondoux]

Hi

The sample above is not based on any LabView example, but I can indeed reproduce the problem with the “Basic DMA - R Series” example.
ModelSim outputs the same error message.

If this may help, with this labview example and the attached test bench, the message is printed every 1.4 µs.

Thanks

[Brice.inno]

Hi

What version of the LabVIEW 2010 FPGA Module's Xilinx compilation tools are you using ?!

[fbondoux]

The NI setup says it's version 11.5.
I can reinstall in case it got somehow corrupted.