PXI-6120 Digital output frequency

[sokal]

Hello,

before I post my question some technical background:

labview: 2011.

PXI-6120 8 digital I/O.

I have read the user manual and search the forum and there is no reference to digital output frequency (only for a counter).

My question is what is the maximum frequency I can generate from digital outputs?

The best I could do is 50 kHz using the example.

Thanks,

Sokal

[crossrulz]

According to the prduct page (https://www.ni.com/en-us/support/model.pxi-6120.html), the DIO max clock rate is 10MHz.

[sokal]

Thanks for the fast reply.

That is correct max DIO clock rate is 10MHz.

But I am interested in digital output (DIO0-DIO7) maximum frequency not the counter (clock).

Thanks,

Sokal 

[crossrulz]

The max counter rate is 20MHz.  It's right there in the specs.

[sokal]

At first I thought that too after I read the data sheet,

but that didn't work in practice so I look for additional information and found the user manual (added file). 

If you look on page 94 you will see that the digital output (8 channels) and the counter or a clock (timing I\O - 2 channels)

are two different things and they have different physical channels (pins).

So my question remains:

What is the max frequency of digital out (page 38 - connection pins 52,17,49,47,19, 51,16,48)?

[Mcdan]

sokal,

The 6120 is capable of producing digital output at rates of up to 10 MS/s.  What error are you seeing?  If you're seeing some sort of a device fifo underflow (-200016 or -200621), then see what happens if you generate more than 190 samples per write. For the sake of experimentation, try modifying 'Create DO array' to generate 100 periods rather than one (for loop with build array set to concatenate mode).  This will create a much larger buffer on the host, and hopefully will allow DAQmx to transfer data to the device far more efficiently.

Hope that helps,

Dan

[Kevin_Price]

Short answer: with a max output rate of 10 MHz, and the need for 2 digital states per cycle, the max freq you can generate on a DO line with that board is 5 MHz.  In general, you can generate integer divisors of the clock rate.

The advice from Dan (Mcdan) sounds exactly right to me.  I'm not on LV2011 and can't see your code, but also have to wonder if you might be running a tight software loop to toggle digital state rather than setting up a hardware-clocked and buffered task. 

-Kevin P

[sokal]

That is good thinking Dan, 🙂

but, the problem is the more points is generated the more the frequency if dropping. Here some of the result of me runs.

The result of me test:

1000 point give me 10 kHz

 500 point - 20 kHz

 190 point  - 51.2 kHz

If I try make a smaller array I don't see any thing - I measure the result with scope - the scope is physical connected to the output ,the scope is capable to measure high frequency - at least 200 kHz.

And, Kevin P.

You absolutely right at you approach, but my goal is to generate signals (PWM) out of digital output without using any counter\clock (only use is for synchronization) the reason for this is simple, on this devise there only two clocks, that mean in theory ( and practice 🙂 ) I can make Only two PWM at high frequency (more then 50 kHz) and it is a serious limitation, 

For over come this limitation I am trying to explore the limitation of the digital out.

For example let say I will need 3 or 5 PWM at high frequency let say 200 kHz (or more) and use the clock only for synchronization, what then should I do?

to answer this question I am exploring the limitation of the hardware.

any information will be helpful,

thanks, 

sokal.

[Mcdan]

sokal,

What are using for your sample clock source? 'MasterTimebase' is a 20 MHz signal, which is above the 10 MHz allowed for DO on the 6120.  Are you seeing errors from DAQmx, or are you not seeing the expected PWM signal on your digital lines?  My prior response was based on the assumption that you were seeing DAQmx errors.  Looking at the frequencies you listed in your results, the frequency is proportional to the length of the write.  To me, this would imply that rather than duplicating a single period of your data multiple times, you stretched your single period over more samples.  If you have a constant sample clock rate, this will effectively slow the output signal.

My questions:

1) Do you get a DAQmx error when running your task?  Note: can you place a 'DAQmx Is Task Done.vi' after the event structure in your for loop?  Your VI as written would not report an error unless you actually changed a duty cycle as written.

2) Are you using 'MasterTimebase' for your sample clock source?  If so, can you modify it to use something else?  You can create a dummy AI or AO task, or use one of the 6120's counters to generate a signal of know frequency.

3) What is the observed behavior of the output?

If I understand your attached VI, you're trying to generate a signal of fixed frequency and modify the duty cycle as it runs.  What is the frequency you're trying to generate?  If I find myself with some spare time this evening, I can see if I can write up an example of this for you.

Dan

[Mcdan]

sokal,

I've modified your VIs as I would given how I understand your VI (saved for LV 2010).

I hope that helps,

Dan