Netlist error in 74LS74 flip-flops

[RnDMonkey]

The 74LS74 model info has a type which causes a Netlist error, halting simulation. The problem happens if you try to place section B, and is because of the following typo in the Symbol to Pin Mapping:

a%p_b[%t2D?%t:d%t;2D
+      %t~2PR?%t:d%t;~2PR
+      %t~2CLR?%t:d%t;~2CLR
+      %t2CLK?%t:d%t;2CLK]
+     [%t2Q?%t:d%t;2Q
+      %t~2Q?%t:d%t;~2Q] %m

should be:

a%p_b [%t2D?%t:d%t;2D
+      %t~2PR?%t:d%t;~2PR
+      %t~2CLR?%t:d%t;~2CLR
+      %t2CLK?%t:d%t;2CLK]
+     [%t2Q?%t:d%t;2Q
+      %t~2Q?%t:d%t;~2Q] %m

Subtle, but that space is important. I don't know what other ICs have this problem, but that's not my job, is it? 🙂

[nestor-sg]

Thanks for reporting this to us. I created a defect record ID 111676, you can use it for future reference.

[RnDMonkey]

Cool beans.