Engine Simulation Toolkit Feedback

[bneaves]

Always been there, but thats just the way i thought to pull it together

Removed it now but now get a different error, i guess i need ot go back and try again rebuilding from scratch

• Start Date: 04/01/2016 20:19

• Loading System Definition file: C:\Users\Public\Documents\National Instruments\NI VeriStand 2015\Projects\HiLRig2015\HiLRig2015.nivssdf

• Preparing to deploy the System Definition to the targets...

• Compiling the System Definition file...

• Initializing TCP subsystem...

• Starting TCP Loops...

• Connection established with target Controller.

• Sending reset command to all targets...

• Preparing to deploy files to the targets...

• Starting download for target Controller...

• Opening WebDAV session to IP 192.168.40.201...

• Processing Action on Deploy VIs...

• Gathering target dependency files...

• Downloading HiLRig2015.nivssdf [58 kB] (file 1 of 4)

• Downloading HiLRig2015_Controller.nivsdat [122 kB] (file 2 of 4)

• Downloading CalibrationData.nivscal [0 kB] (file 3 of 4)

• Downloading HiLRig2015_Controller.nivsparam [0 kB] (file 4 of 4)

• Closing WebDAV session...

• Files successfully deployed to the targets.

• Starting deployment group 1...

* * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * *

The VeriStand Gateway encountered an error while deploying the System Definition file.

Details:

Error 1124 occurred at Project Window.lvlib:Project Window.vi >> Project Window.lvlib:Command Loop.vi >> NI_VS Workspace ExecutionAPI.lvlib:NI VeriStand - Connect to System.vi

Possible reason(s):

LabVIEW:  VI is not loadable.

In a built application, this error might occur because the VI being loaded was last compiled for a different OS or with CPU features, such as SSE, that this target does not support. In this case you must rebuild the application for the target OS and make sure SSE compiler settings in the build specifications match the target platform. This error also might occur if the VI is a polymorphic VI, which cannot be loaded in the LabVIEW Run-Time Engine. You must load an instance of the polymorphic VI instead of the polymorphic VI itself.

=========================

NI VeriStand:  Open VI Reference in NI VeriStand Engine.lvlib:Open Custom Device Driver VI Reference.vi->NI VeriStand Engine.lvlib:Launch Asynchronous Custom Device.vi->NI VeriStand Engine.lvlib:VeriStand Engine State Machine.vi->NI VeriStand Engine.lvlib:VeriStand Engine.vi->NI VeriStand Engine.lvlib:VeriStand Engine Wrapper (RT).vi<APPEND>

c:\ni-rt\NIVeriStand\Custom Devices\Engine Simulation Toolkit\Engine Simulation Toolkit Engine Pharlap.llb\RT Driver VI.vi

* * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * *

• Sending reset command to all targets...

• Stopping TCP loops.

Waiting for TCP loops to shut down...

• TCP loops shut down successfully.

• Unloading System Definition file...

• Connection with target Controller has been lost.

[Joel-P]

Hello bneaves,

This sounds similar to the issue that I noticed with the first version of the built custom device where the VxWorks.llb was being set as a dependent file for a Linux_32_Arm target.

I would like you to try a new vsproj/nivssdf, use the same target and bitfile, and then attempt to deploy.

You could also look in the sysdef xml to see if you are getting a similar problem with the XML, I copied in the offending xml a couple posts ago.

As a quick note, I saw the incorrect .llb being deployed when I had the v2 build installed. The system definition had been built with the first version of the build, then I updated to the v2 build, and the problem still occurred. However, when I built a new system definition and used the same bitfile, there were no issues.

I am not sure why the system definition specified an incorrect .llb, it's something that I'm looking into.

I am very interested to know if you build a new test vsproj and system definition and this issue persists.

[bneaves]

Hi

Tried a few things, including a new project, but no improvement unfortunetly

If i look at the content of the various llbs for each target operating system the Pharlap has totally different contents to all of the others.

The llb listed on the left is the one that is being deployed to the target

If i rename one of th eother llbs to be Pharlap I then get an error saying incorrect operating system when trying to deploy

[bneaves]

Have rolled everything back to 2014 and all working fine as expected

Please let me know when you have any news on 2015

[Joel-P]

Hello bneaves,

Something odd happened on the v2 build. You were right that the RT Driver VI wasn't included, but I am not sure why that built incorrectly.

I built v3 which has the correct pharlap.llb and placed it on the community page.I tested this on my PC and the custom device worked correctly for a phalap target.

Let me know if you run into anything on that build.

[ikc]

Hi Joel,

I am new to VeriStand and trying to use this Engine Simulation Toolkit with VeriStand 2014 SP1.

I built the bitfile, defined the digital pattern.

However, I don't know how to run it in VeriStand.

We are using 7854R on PXI.

Show me how to output crank angle on Connector0/DIO0 would be of great use.

Could you provide us more detail like simple how-to-ues guide in VeriStand?

Thanks a lot,

ikc

[Joel-P]

Hello ikc,

To use Connector0/DIO0 you need to wire the output of the of the Digital Pattern Generation.VI to that FPGA I/O Node. I would highly recommend that you start from a copy of one of the example VI's which can be found in the Engine Simulation Toolkit Examples.lvproj which is available here C:\program files (x86)\ National Instruments\LabVIEW 2014\Examples\ NI\ Engine Simulation Toolkit (EST)

Once you have completed, and compiled the bitfile for your target, then you need to have the Engine Simulation Custom Device installed for VeriStand. Then you can add that custom device to your target in the VeriStand System Definition, and select your bitfile in the custom device. Once the bitfile is selected and the APU is added you can add your Digital Pattern to the custom device.

Once you have those settings configured you can deploy your system definition to your RT PXI, and the digital pattern that you created will output based on the Desired Engine Speed channel. If you want to start at a specific angle, you can specify that in the APU Settings page.

Once this is running you can monitor the Crank Angle channel to read the current value.

Best Regards,

Joel

[ikc]

Thank you, Joel.

I appreciation your detail response. This short explanation is very useful to us.

It means that to observe the Crank Angle on Connector0/DIO0. I need to do the following steps.

Installation:

1. VI package(Engine Simulaton Toolkit) installed on LabVIEW

2. Engine Simulation Custom Device installed on VeriStand

Implementation:

1. Build the bitfile in LabVIEW FPGA project

2. Add custom device to VeriStand by selecting the above bitfile

3. Add Digital Pattern

4. Set "Desired Engine Speed" value

5. Monitor "Crank Angle" in the workspace or scope

Best Regards,

ikc

[This_is_my_alia]

Hello,

We are using the Engine Simulation toolkit and it is working great. We were only using one CAM signal but now want to add a second one. However, when we look at the Custom Device for the Engine Simulation Toolkit, the 'Add CAM' button is grayed out so we can't add it. We have some FPGA code that we have modified to generate a second CAM signal using the appropriate names for the Veristand custom device for the CAM configuration but alas the Veristand model won't even deploy.

Any advice you have for adding a CAM signal to our Veristand project would be appreciated.

[Nicopsa]

Hello Joel,

We are using Engine Simulation Toolkit too, it works well and we are really proud of it. The O2 sensor simulation really interests us, did you plan to include it, in your next software release ? Moreover, do you know when it will be available ?

Best regard.