Has anyone implemented the SPI bus on a 7831R using Labview 2009? I

[Eletrostatic]

Regarding my question on having the SPI signals and CS on the same ports. This was doing because the hardware team specified the interfaces and did the prototypes without consulting me . As in the example the SPI signals are on Connector 0 DIO pins and CS are on connector1 ports. I therefore only have only 1 connector to (predefined DIO0 to DIO11) to have all of the signals and CS's for the SPI buses. Perhaps some confustion between connector/ports on my part.

Thanks....

[Eletrostatic]

Does anyone know if you can inspect the SPI messages without any slave devices connected.

I now have 3 versions of the SPI driver made and I do not see anything on the SPI lines when I write a message.! I was thinking perhaps slaves are needed to complete the system to get any information moving.?!

[smithd]

Hey Electrostatic,

As far as my understanding of SPI goes, it should output a signal regardless of whether or not slave devices are connected. However, since you are programming the system yourself, it is impossible to know what will or will not happen without looking through your own code. My suggestion would be to run the FPGA with simulated IO and use our labview debugging tools like probes and highlight execution to look through your code. For more info on simulate I/O, take a look at this document (especially the last picture, since you do have a real RIO system to connect to already):

http://digital.ni.com/public.nsf/allkb/F466AD83D24F041D8625714900709583?OpenDocument

This may also be helpful:
http://zone.ni.com/reference/en-XX/help/371599D-01/lvfpgaconcepts/test_bench_tutorial/

Thanks,

D Smith

[Eletrostatic]

I do not have any issues measuring from the FPGA or asserting lines or even generating a fixed frequency output.

However I still cannot get the SPI example to run. NI support are looking onto my problem at least. Running PXI-1033 with 7813R with windows 7 (DS 2010)

[Eletrostatic]

When you compile the code on a FPGA you define the Top level of the code!

However when I compile the code and it runs if I open the port block with the top level its not running, if I click to start its says its not included?!?!

Can some explain to me what this means !?

Thanks ;( 

[smithd]

Hi Electrostatic,

Can you please clarify what error you are seeing? If I am reading this correctly, you have a host FPGA VI and some subVIs, you have compiled the hostFPGA VI and it runs. What I am not sure about which 'port block' is not running, or not included.

Thanks,

D Smith

[Eletrostatic]

I am out of office till tomorrow, so I will check this as soon as I get to work.

The example SPI I am using has a top level that has the read/write state machine with a subVI called SPI port (Its the SPI port driver).

I assume it calls the subvi in the FPGA if its requested. I wanted to check that data is moving in the FPGA while the top level and PC host VI's are running. (So I put some indicators to check). But when the top level is executed and I open the Subvi (PORT SPI) it looks like thats nor running as th arrow is not depressed. Not sure it thats normal or not.

Anyway I will check the error I get when I try to execute the subVI while the Top Level is executing and let you know...

Thanks...

P:S. I have one extra question I just remebered. Is it possible to modify the SPI port driver to accept a element of 32-bits.? Now it works with 8-bit elements where you specify the max bits in a frame prior to writing. Our firmware guys where hoping it would be possible to write one element of U32. Otherwise we have to fragment our messages.

[smithd]

Hey Electrostatic,

SubVIs in an FPGA are not subVIs in the way you expect from labview. They are flattened out by the labview compiler--there is not part of the FPGA you can point to and say, this is the subVI. All of the indicators, etc. on the front panel of an FPGA subVI do not exist, they are essentially replaced with wires. I am not surprised that the subVI is not running. However, if you run the VI in simulation mode, you may have better luck at troubleshooting.

As to your second question, if you look at figure 5 in your original document, it looks like you specify the number of bytes you wish to write. Since it sends the data out in serial, it shouldnt matter how long your signals are.

Thanks,

D Smith

[Eletrostatic]

Hi,

So I finally got some activity from the SPI driver. However few issues still persist...

I have set my wait ticks to 1. CS goes low and 1 cycle passes before SCLK starts. However SCLK stops the same time CS goes high again. This needs to be symetrical. 1 tick between the SCLK and CS on either side.

I have to restart the FPGA every time I send a message. It gets stuck somehow and new messages will not be sent without a restart of the HOST and FPGA VI's

Thanks for any help....

[smithd]

Hey Electrostatic,

So I've been looking through that original document and I notice there are a number of locations where the wait time is decremented. Do you still see the same result when you set the wait time to 2 or 3? If so, maybe you can remove one or more of the decrements (this may take some logic-fiddling) and see if that resolves the issue. It is difficult to see where that SCLK value is changed. I think I've looked through every case, but I still can't find it. Are you able to locate it?

Thanks,

D Smith