Problem of Timed-Loop Timing and Sampling 60Hz Signals

[Amir 2011]

Hi there,

I am trying to sample a 60Hz signal with a rate of 1200 Hz and do Fourier FIR filter with 20 samples to extract its real and imaginary parts and then calculate the RMS value etc. 

The problem is that the loop rate is 1200 Hz and the corresponding period will be 833.33333 us. How ever LabVIEW Timed-Loop only accepts integer values for the period and the closest is 833us. But this corresponds to 1200.48 Hz and causes problems/inaccuracies for my measurement. 

For Fourier Filter my sampling rate has to be an integer multiple of 60 and such a rate is not an integer period in terms of Timed-Loop.

In a nutshell, I need a loop rate of exactly 1200Hz, which seems impossible with the Timed-Loop.

Is there a way around this problem? 

Thanks

[Pie56694]

You may be unnecessarily coupling acquisition with processing.

The acquisition you described runs at 1.2KHz. The processing algorithm you described consumes 20 sample points at a time. If that data is sampled at 1.2KHz, then the processing algorithm needs only run at 60 Hz. If you decouple the acquisition from the processing, then the "integer multiple of the timing source" caveat to Timed Loops doesn't matter.

In DAQmx for example, you might configure a continuous analog input task at 1200 Hz with (N * 20) samples to read, where N is an integer >= 1. The processing loop need only run >= (60 / N) Hz, and you'll program parallel operations on each 20 sample block of data returned by the DAQmx Read VI.

Another DAQmx option would be to utilize the DAQmx Create Timing Source VI to hardware time the processing loop. You'll find an example in <labview>\examples\DAQmx\Control\Control.llb\PID Control-Control Loop from Task.vi.

- Steve K

[Amir 2011]

Hi Steve,

Thanks for your reply. 

The problem is data acquisition. Processing is easy if I could sample data with a rate of exactly 1.2kHz. 

I am using NI9215 to sample data in the FPGA with the rate of 4800 Hz. Then I downsample it to 1.2kHz. RT reads data from FPGA with a period of 833us which corresponds to 1200.48 Hz. The problem is that the Timed-Loop does not provide the period of 833.33333us that corresponds to 1.2kHz. 

Is there any other clock that can be used to have 1.2kHz? (I have to use 1.2 kHz because the sampling rate has to be a multiple of 60 Hz)

Thanks

Amir

[Pie56694]

Hi Amir,

Some hardware exposes the ability to drive LabVIEW diagrams from external timing sources; cRIO does not.  Even if you had access to an internal timing source capable of driving the loop at exactly 833.333333us, it wouldn't run at exactly that rate each iteration due to the nature of the real-time operating system.  Would you post some code or screen shots showing what you're trying to do?  You might find use in the NI CompactRIO Waveform Reference Library.

- Steve K

[Amir 2011]

Hi Steve,

Thanks for clarifying that this a cRIO limitation and there is not much I can do about it. It is very unfortunate though. 

The code is extremely simple. Just pit a simple Timed Loop in RT and try to run it with 1200 Hz. You will see it is impossible!

Amir

[Pie56694]

Hi Amir,

I claim it's not a limitation in any application that's been properly paired with the cRIO platform because there are architectures that support the requirement you provided.  Perhaps I'm missing something.

- Steve