Hi there,
A simple one:
I
have a RT application where I transfer small amounts of data (around
1Kb) between 5 FPGAs (7813R) and a microprocessor (8106RT) at high
speed (2KHz). The data is used to implement a closed loop control
system, so I really ned new data available in the uP each 500us.
Ideally for the stability of my system I would need to do all the
reading, processing and otputs writting in less than 100us.
DMA FIFOS don't seem to be a good option for this application and the Read/Write block have proben to be too slow for my requirements (around 100us to read from FPGAs, 70 us to write to FPGAs)
Do
I have any other option for doing this data transfer? Is there any way
of using lower level code/instructions other than this Read/Write
blocks and implement a faster communication
Cheers,
Jose
