error code -1073741515 FPGA compile

[FSAENZ]

Hi, looking for some advice on an error that has started occuring in FPGA compiler. I haven't use LV for quite a few months and came back to try a very simple analog to frequency circuit using cRIO and got the error. Everything was working fine last time I used it.

I made a vi with just a while loop and tried compiling that and same thing happened so I'd be reasonably sure it isn't a problem with the vi. Couldn't find any other info on the error code on the web. Also tried doing a repair of all LV software from the add/remove panel but no improvement. I haven't done a mass compile yet tho. Using WinXPSP2 and LV8.1 on a Dell dual-core notebook.

The last few lines of the compile report are as follows, I can supply the whole report if needbe.

Thanks,
Andy.

#----------------------------------------------#
# Starting program map
# map -o toplevel_gen_map.ncd -intstyle xflow toplevel_gen.ngd toplevel_gen.pcf
#----------------------------------------------#
Using target part "2v1000fg456-4".
Mapping design into LUTs...
Running directed packing...
Running delay-based LUT packing...
Running related packing...

Design Summary:
Number of errors:      0
Number of warnings:   92
Logic Utilization:
  Number of Slice Flip Flops:         304 out of  10,240    2%
  Number of 4 input LUTs:             337 out of  10,240    3%
Logic Distribution:
  Number of occupied Slices:          249 out of   5,120    4%
  Number of Slices containing only related logic:     249 out of     249  100%
  Number of Slices containing unrelated logic:          0 out of     249    0%
        *See NOTES below for an explanation of the effects of unrelated logic
Total Number 4 input LUTs:            340 out of  10,240    3%
  Number used as logic:               337
  Number used as a route-thru:          3

  Number of bonded IOBs:              148 out of     324   45%
  Number of GCLKs:                      2 out of      16   12%

Total equivalent gate count for design:  4,688
Additional JTAG gate count for IOBs:  7,104
Peak Memory Usage:  119 MB

NOTES:

   Related logic is defined as being logic that shares connectivity - e.g. two
   LUTs are "related" if they share common inputs.  When assembling slices,
   Map gives priority to combine logic that is related.  Doing so results in
   the best timing performance.

   Unrelated logic shares no connectivity.  Map will only begin packing
   unrelated logic into a slice once 99% of the slices are occupied through
   related logic packing.

   Note that once logic distribution reaches the 99% level through related
   logic packing, this does not mean the device is completely utilized.
   Unrelated logic packing will then begin, continuing until all usable LUTs
   and FFs are occupied.  Depending on your timing budget, increased levels of
   unrelated logic packing may adversely affect the overall timing performance
   of your design.

Mapping completed.
See MAP report file "toplevel_gen_map.mrp" for details.



#----------------------------------------------#
# Starting program par
# par -w -ol std -intstyle xflow toplevel_gen_map.ncd toplevel_gen.ncd
toplevel_gen.pcf
#----------------------------------------------#
ERROR:Xflow - Program par returned error code -1073741515. Aborting flow
   execution...

[CarlaU]

Hi Andy,

There are few different things that could be causing this FPGA compilation error. The first thing that comes to mind is that it could be due to a version conflict. Which version of LabVIEW and which version of LabVIEW FPGA are you using? You need to be using the same versions for each (i.e LabVIEW 8.0 with LabVIEW FPGA 8.0 or LabVIEW 8.2 with LabVIEW FPGA 8.2).  Also, which version of the RIO driver are you using? One suggestion that you could try is compiling one of the FPGA examples from the NI Example Finder. This would help determine if the error is occurring due to your specific code or something to do with the LabVIEW software/environment. I hope this helps!

Carla

[FSAENZ]

Hi Carla,

Thanks for the reply. I found a temporary solution by dusting off an old desktop and running the compile on that. it worked fine and has exactly the same versions of everything on it. LV8.0.1, FPGA 8.0.0, RIO 2.3.1.

I might do a full reinstall if nothing easy.

Thanks,
Andy.

[CarlaU]

Hi Andy,

Thanks for your response. I agree with your suggestion. I think that the best thing to do would be to do a complete uninstall and reinstall. My guess is that something must have gotten corrupted or not installed completely. Please keep us posted with the results. Have a great weekend as well!

Carla

[fernholz]

I just encountered exactly the same problem.
I wanted to compile a program that compiled before with the above result.
I created a new project, with the simplest possible FPGA architecture: connecting a true/false input to an output line.
Again, the same error.

After a brief research on the web for this error code, i found some descriptions of cases with MS Visual Studio, when apparently some resource could not be initialized.

Did Microsoft recently release a Windows update that might have been installed automatically (or some other person than me), which causes this problem?

Best,
Thomas

[CarlaU]

Hi Thomas,

I'm not sure about any issue regarding Microsoft but it is a good theory. I have not seen any other issues that are similiar to this regarding it so far though. Which versions of LabVIEW and the LabVIEW FPGA module are you using? I would suggest that you take a look at the known issues of the FPGA module to see if anything sounds like it could pertain. Like I said earlier in this thread, you might just have to do a complete uninstall and reinstall of the software. I hope this helps.

Carla

[gogomac]

Hello.
The same error is given to me. I cannot compile even simple vi only for WHILE loops.
Please teach the cause why this error occurs. The environment is LabVIEW8.5.1, RIO2.4, FPGA8.5.1.

There was not an effect even if I deleted a tmp file of FPGA in the C drive.

I uninstalled three software. I installed it in the back once again, but was not able to compile it.

With 8.2.1 of FPGA installed in the same PC, I can compile it without a problem.

=======================
...............
Writing NGDBUILD log file "toplevel_gen.bld"...

NGDBUILD done.



#----------------------------------------------#
# Starting program map
# map -o toplevel_gen_map.ncd -intstyle xflow toplevel_gen.ngd toplevel_gen.pcf
#----------------------------------------------#
ERROR:Xflow - Program map returned error code -1073741515. Aborting flow
   execution...
=======================

[fernholz]

Hello,

I was able to solve the problem by first deinstalling and then reinstalling the Xilinx tools, which come as part of the FPGA software module.

The procedure was not very straight forward, though. The install wizard got stuck a couple of times.

Good luck,
Thomas

[gogomac]

Hello, fernholz,

Thank you for advice.
There is a question about a solved method. Did the tool of Xilinx install it from a CD of LabVIEW FPGA? Or will it be the tool which it downloaded from Xilinx?
In the case of the tool which you downloaded from Xilinx, will you teach URL?(or name/Version)

Thanking you in advance.

[fernholz]

Hello Gogomac,

The Xilinx tools that I reinstalled are part of the Labview FPGA module.
You will have to choose the custom install options and then find the Xilinx tools in the option tree, i.e. those grey or white boxes with the triangles where you choose which
modules, languages, etc. you want to install.

But I used LabView 8.0 and Labview FPGA 8.0.
I don't know, if the structure in LabView 8.5 is still the same.

Best,
Thomas