how to use HIL with quarter car suspension system with crio

[wgkotb]

I have built a labview model for 2 DOF car suspension system and run the simulation off line.

I want to build hardware in the loop (HIL)  for the same model but want to use AO and AI to send signal to a real damper and measure it force and velocity the acquire these two signals via AI and input it to the model.

Is there any tutorial to start with building the HIL model integerated with the crio and FPGA

[Josh_E]

Hi wgkotb,

It sounds like an interesting project you're working on there.

You could use the FPGA to acquire the data and do HIL testing. You could then send data from your FPGA to the cRIO Real Time controller for data logging or more complex analysis.

As such you will need to build a Real-Time project. This project could contain an FPGA VI that does the HIL testing and a Real Time VI that does any logging or data presentation.

The first link below contains some good information on using a Compact RIO without using the FPGA (Scan Interface). Once you're comfortable with this, the second link provides some information on using LabVIEW FPGA.

https://decibel.ni.com/content/docs/DOC-15882 

https://decibel.ni.com/content/docs/DOC-15882 

I hope this is helpful.

All the best!

[wgkotb]

Thanks Josh,

It is a good to start with these information.

Could you please confirm the second link you recommedned as it seems the two links are the same

[Josh_E]

Hi wgkotb,

Sorry about that, here's the correct link I meant to include.

https://www.ni.com/en/shop/electronic-test-instrumentation/add-ons-for-electronic-test-and-instrumen...

All the best,

Josh

[Lozoya]

Dear Josh

We already do this: the FPGA perform the acquisition of the real damper force, computes the quarter of vehicle state space representation, and send the four states to four analogu output. Using FIFOS we send eight signals to a vi in real time module, to logging and presentation. 

The problem is present with the fixed point operations in the FPGA. We will test now the computing of the quarter of vehicle in the rt vi and only the acquisition / analog output in the FPGA.

The equipment is a NI 9004 cRio with  NI 9263 analog output.

Could you give us your opinion about this configuration?

Best regards

Jorge de Jesus Lozoya Santos

Tecnologico de Monterrey, Mexico

[Josh_E]

Hi Lozoya,

Setting up your HIL control on the FPGA and passing data via FIFOs up to the Real Time VI is definitely a method I would recommend!

It means all the processing of the control is outsourced to the FPGA, freeing up the Real Time processor for other tasks.

It's a shame you had some issues with fixed point operations on the FPGA; This can often be a source of issues, and understanding how to use them isn't always easy.

However a safe method I use to get complex computation working on an FPGA is as follows.

1) Start with the bare minimum on the FPGA, just enough to pass data up to Real Time.

2) Start prototyping your control algorithms on a Real Time VI (prototyping on Real Time means you can make edits to your algorithm without having to wait for a compilation).

3) Once you're satisfied with your algorithms on your Real Time VI, try to start encapsulating parts of the code on Real Time. If you can identify the fundemental parts of the code and put them into sub-VIs, it will make it easier to translate the Real Time code into FPGA code later.

4) Now you should have a Real Time VI composed of separate code 'chunks'. 

5) Recreate each code 'chunk' on the FPGA. Once you've finished a code 'chunk' on FPGA, test how it behaves related to the Real Time equivalent. This way you can identify any issues on FPGA, before things get too complicated. 

It is at this stage that you need to pay attention to fixed point values. Remember, you must specify the range and the delta of every fixed point number on FPGA. A lot of issues on FPGA are often caused by not selecting the correct ranges for fixed point numbers, resulting in numeric overflows, and incorrect program behaviour. Since you've already prototyped your code 'chunks' on RT, you should be able to ascertain the ranges and delta for each value in a calculation. Use this to your advantage and be careful when selecting the properties of the fixed point values.

6) Build up your FPGA code by linking your code chunks together. 

Although this method can take longer than simply coding on the FPGA to start with, it can prevent any troublesome issues and reduce the amount of FPGA troubleshooting you'll need to do.

I hope this helpful, good luck!

[Jack623]

The issue is existing with the set factor functions in the FPGA. You may analyze now if the processing of the one fourth of automobile in the rt vi and only the purchase / analogue outcome in the FPGA . . . . . . . . . . .

[wgkotb]

Dear Lozoya,

I'll do a project like you and I need to know how to acquire data via FPGA and make a controller in RT VI and then generate AO via FPGA using CompactRio 9022 and AI 9215 and AO 9263

Cheers

[wgkotb]

Dear Josh,

I already do the project to acquire 3 AI via FPGA and do not know how to access data and use AI as a part of my controller i.e. make some math on acquired AI and then generate AO to be written on FPGA.

Could you please tell me How to accesss AI and use then to generate AO

Thanks

[Josh_E · Accepted solution]

Hi wgkotb,

Are you passing your 3AI signals from FPGA up to your RT host? If so, you could do the mathematics on the RT controller, and generate the AO values to send to the FPGA.

Alternatively, are you wanting to have your FPGA VI calculate the desired AO values?

Kind regards,