LabVIEW FPGA Idea Exchange

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Relative Paths for Xilinx IP

When using the Xilinx IP nodes in LabVIEW FPGA it becomes very difficult to support source code control and branching. The biggest issue is the fact that the "Folder for Support Files" entry is absolute. So when we need to branch the code to isolate new feature development from the main trunk the relative path is now wrong. Please make this and all other paths relative to support a more robust development environment.

Add a common part for FPGA Palette

Memory Initialization VI Input

Memory initialization is one of the more tedious aspects of LVFPGA coding. A lot of my LVFPGA vis have multiple memory elements that I need to access simultaneously for a given operation. I've tried to streamline the initialization process by making all memory initialization vis read from an init values file and populate the array indicator. However now I have to have multiple initialization vis reading from different points in the same init values file. If I could somehow get a parameter into the memory initialization vi, I could programmatically select from where in the init values file to read. Here is how this could work:

Save FIFOs in a library

Currently, in LabVIEW you can right click a VI's icon at the top right of the front panel to find all instances including where the VI is referenced in a static reference node. Also, when you use have a "Open FPGA VI Reference" in "build specification" or "VI" mode, you can double click the node to open the referenced block diagram. Once the FPGA front panel is open, there's no easy way to get back up to the caller. It would be cool if we could extend the right-click-find-all functionality so that when you right clicked a top level FPGA VI, it would search where that VI was referenced in any "Open FPGA VI Reference" nodes. Currently, when you right click and search, it just says no instances found.

Having two computers, one for developing and one desktop pc for administrative work, I use the desktop as compile server for compiling the FPGA VIs. The compilation takes about 45 minutes, during which I can't develop anything in LabVIEW. By sending the data to the desktop pc, I can resume my work. Though on the desktop machine it's annoying to always leave this program open and get closed accidentally from time to time or I forget to start it in the morning after booting the pc.

Suggestions:

- Minimize the LabVIEW FPGA Compile Server to system icon tray

- Option for starting the Compile Server on booting of the OS.

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Connector Name

While attempting to debug NI1483 issues, I found it necessary to make modifications to the NI1483 CLIP. In LabView 2014 and earlier, it's not possible to maintain your own IO Module CLIP directory. One must maintain all IO Modules within the IO module search path (<National Instruments>\Shared\FlexRIO\IO Modules folder ). This can be done by copying an existing IO module to a new path within the <National Instruments>\Shared\FlexRIO\IO Modules folder, then editing the *.tbc file to rename the "model" key. The main issues with this approach are the potential lack of administrator permissions and the difficulty of maintaining source control in a non-project related system directory.

The suggestion is thus:

1. Give the user an option to select the path of the IO module under the IO module Properties General Category (When Enable IO Module is selected).

That's it!

I find myself again and again having to memorise bit field index and other things in order to be able to debug FPGA code efficiently. What I would really like to be able to do is to create an XControl with a compatible datatype (Say U64) and have this display and accept input in the form of human-readable information.

The data being transported is simply a U64 and the FPGA code doesn't need to know anything about the XControl itself. Just allow a host visualisation based on an XControl to ease things a bit.

I've already started using LVOOP on FPGA and I think this could be another big improvement in the debugging experience. Having an input XControl (or a set of XControls) for certain LVOOP modules on the FPGA just gets me all excited.

Prompt for Fixed-Point Configuration

I know that when connected to the compile server the local compile status window will show you when a compile is done, however that does seem to severely limit productivity in that the only way you can get back to working in LV is to disconnect from the compile server. The downside is that you don't get any feedback as to when your compile has completed. This is especially true if your compile server is running on a remote machine.

Why not add a feature to LabVIEW to allow disconnecting from the compile server but still provide a background polling feature to update the user when the compile has completed. Something as simple as a dialog box telling me that my compile is ready would be great. It would allow me to get back to work on other sections of the code while still closing the loop on the running FPGA compile process and alerting me that it is done.

If the system polled once every minute or so that would be more than adequate.

Offset Shift Registers

Support malleable VIs in FPGA targets

I work with malleable VIs a lot on desktop. They can save a lot of boilerplate code. From my understanding, the entire feature has no effect once code is compiled: the VI is converted to an "instance" VI with the proper data types and inlined into the caller. This doesn't seem like it should be problematic to use on an FPGA target.

Here are a few FPGA-specific wins that I think VIM support would deliver:

Array size adaptation
- One can imagine writing a "parallel for loop" VIM that simply expands out N parallel iterations for array sizes 0-N
Fixed point configuration adaptation
- Without VIM, if you write a VI that operates on fixed point numbers, it will auto-coerce to the configuration on the controls of the VI

LabVIEW FPGA Host Interface

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Unified Functions Palettes

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Hello,

Is there any possibility to use a dedicated file to change the Number of Synchronizing Register

Today we need to right click on the DIO + Propriety + Advanced Code Generation + Select Nb of register.

On a SBRIO 9607 I have to do it 96 times and if I change something with the CLIP generator I need to do it again.

In my design I use VHDL IP so the synchonisation is already done on the VHDL and I don't need extra clock.

I try to edit with Notepad++ the .lvproj file and change the NumberOfSyncRegistersForReadInProject or NumberOfSyncRegistersForOutputData but it's not clean...

If you have an idea it will save a lot of click.

Thanks

LabVIEW FPGA Idea Exchange

Relative Paths for Xilinx IP

Add a common part for FPGA Palette

Memory Initialization Browse Button Default

Memory Initialization VI Input

Configure Memory / FIFOs from Outside FPGA Target Scope

Save FIFOs in a library

Extend right click find all instances functionality to finding where the FPGA VI is opened

Array to number coercion dot when sign extending

Minimize FPGA Compile server to icon

Connector Name

FPGA global variables accesible through Desktop Execution Node

Allow project hosted IO module CLIP

XControls on the FP for interactive debugging

Prompt for Fixed-Point Configuration

Prompt the user when an FPGA compile has completed

Offset Shift Registers

Support malleable VIs in FPGA targets

LabVIEW FPGA Host Interface

Unified Functions Palettes

RMC Socket Number of Synchronizing Register