LabVIEW FPGA Idea Exchange

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Currently, LabVIEW does not have the functionality to save the settings of the modules (e.g. cRIO module channel names) so it can be imported into another target. The only option is to copy and paste. This functionality would speed things up significantly when moving from one target (e.g. cRIO-9074) to another (e.g. cRIO-9076) with the same modules or most of the same modules.

Hello,

 

i would suggest some Improvements to the Timing Violations Window.

 

  • Highlight the Whole Path with all Element and Wires in the Blockdiagramm when i click on Path in the Timing Violations Window.mark path.png

Path Highlighted.png

 

  • Highlight the Element on the Blockdiagramm which i clicked in the Timing Violations Window.

   mark element.pngElement Highlighted.png

 

 

  • Give the Problem Window of the Timing Violations Window the ability to adjust its size i often have to scroll. (Can be seen in the Timing Violation Window above)

 

With kind regards

westgate

If I kick off a compile behind my VPN I can't re-connect to the compile when I get back to the office (different IPs?).   I know this isn't a typical use case, but when compiles times or queues are long I kind of have to work around the compiler's schedule (and occasionally work from home). 

Problem:

Auto-Indexing of LabVIEW is extended to LabVIEW FPGA, only with one small caveat. You can easily auto-index into a loop, but not out of it. You will understand this better if you've already worked with LV FPGA.

In the FPGA paradigm, we enforce compile time resource determinism, by making sure all our arrays are of a fixed pre-determined size. In auto-indexing out of a loop, we may not know what the size of the array is, and hence it breaks the VI with the error "Arrays must be of fixed size". Try to write the following code in LV FPGA, for a better picture:

Auto-Indexing LV FPGA

 

Solution:

The current workaround is that we have a fixed size Array which we then use in and out of the loop, replacing its

elements, as shown below.

 

2.PNG

 

However, an easier and much much more intuitive solution for users would be to just right click the auto-indexed tunnel and set the dimension size.

Auto-Index Pop 

 

This definitely means that the number of data flowing out of the loop could be more than our fixed size. We handle that case by providing the user with the "In case of overflow" option.

4.PNG

 

 

This would ease our effort in coding LV FPGA as much as it would would improve intuitive coding. Vote for this idea if you think it would make your life a tad bit easier.

I'd like to have a dedicated FPGA Compile Server, based on a realy slim OS, e.g. damn small linux oder even PharLab? The OS does not realy matter, as far as it is multi-core capable and it should use as little system resources as possible, to get as much ressources as possible for the compilation process.

 

Purpose: get max. compilation speed

 

Better visual indication of estimated and final timings in compilation report.

 

Would it be possible to add some visual clues as to whether a given clock in an FPGA design has been met or not? Maybe a background colour, green for good and red for bad?

 

color clocks.png

Sometimes it's really hard working out which clocks have met timing and which not.

We need to have more FPGA Vision example codes. I followed NI introductory articles on image processing using FPGA and they sound great, but was very much disappointed when trying to find usable examples as there are only 5 examples on the IPNet, far fewer than what the intro articles suggest what FPGA can do. 

With even simple examples we experience errors when trying to run Instruction Framework based LabVIEW FPGA VIs.

 

This is a blocker for our using Instruction Framework.

MGT interfacing to the 7915 is provided: https://forums.ni.com/t5/Examples-and-IP-for-Software/Aurora-64b-66b-Streaming-Example-for-the-PXIe-7915-Ultrascale/ta-p/3952187

 

It is not provided for other cards such as the 5785.  Is the interfacing the same?  Could examples for this be provided?

P2P is a very useful technology for sharing data between NI targets.

 

Could this be provided for GPUs?

One of the benefits of the Instruction Framework is that one could develop several modules each using Instruction Framework.  The modules can then be integrated and the Instruction Framework modules can be assembled using Collections.

 

This information is not clear and the provided tutorial does not provide information on this use case.

To allow the creation of reusable code we can wire references to IO nodes to make reusable subVIs. This principle does not appear to apply to module property nodes such as data rate. Enabling this will increase the scope of reusable FPGA components.

Hello,

Recently, Last year, i've had a bad experience, when i tried to compile my old FPGA applications with Windows 10.

 

=> The FPGA ISE XILINX compiler is no more compatible with Windows 10.

 

Will something be done ? I got no clear answer from NI support ...It should be a XILINX problem !

 

The issue is that some products on the NI web site, are sold without clear information about the incompatibility with Win 10 !

 

Please, add a "clear highlighted Warning" on the product page in order to inform about the problem : On FPGA boards and on CRIO targets ...

 

Thanks for help.

 

When you are using same code on different boards, it would be a big help if you could set the "FPGA VI Reference" indicator as "Adapt to source". When I use dirrerent DMA on different target, then the wire break every time I change target:

 

My FGV for the FPGA reference looks like:

 

FPGA ref Adapt to source.png

When setting up a custom VI to use as a simulation test bench, you are currently limited to setting a constant path. If you move your VI, send it to another user, change the name, or otherwise change the path of the custom VI, you must enter the FPGA target settings and modify the path. That is, if you moved the project below from user1's desktop to user2's desktop, you would have to enter the properties and change the location. This makes code sharing somewhat tedious.

psugg.png

Using a relative path or a project item would make this feature easier to use.

Xilinx supports BRAM primitives (FIFO and normal BRAM) with certain varying width read and write ports.  For some applications, the ability to write 2x 16 bit values to a FIFO in one loop and read 1x 16 bit value from the FIFO at double clock rate in another loop can be very useful.

 

As it stands, the IPCore for such BRAM primitives, although present in LabVIEW FPGA, cannot be used without a CLIP (essentially making this aspect of the IPCore useless).

 

It would be cool if LV would expose the ability to have differing read and write port widths for BRAM.

When setting up memory in LV FPGA these seems to be one important setting missing....description.

 

Good programming practice defines that we should have descriptions in our code, similar to the VI description of a global variable. This would also help out immensely when using bit packed memory blocks to define status bytes and such as the description of the individual bit meanings could be added to the description and not having to be dropped as block diagram comments everywhere one of the nodes is used.

Hello,

 

In Labview 2010, the implementation of INLINE VIs has been improved. But this feature is not aivalable in Labview FPGA.

 

When you are looking for ticks/space you have to replace the VI calls by their content ... and then the FPGA VIs becames rapidly unreadable.

 

I think that inline VI could be very interresting in FPGA because ...

 

 

  • Ability to create userfriendly / updatable / readable / clear FPGA diagrams 
  •  Optimize the time/space needed to call a real VI
By default, FPGA VIs should all be "Inline" VIs !
Manu.

 

Presently, the Xilinx Compile Tools do not appear in the MAX technical report or NI License Manager. As a result, to determine the version, users must go to Add/Remove Programs in the control panel to determine which versions they have installed. It would be great for troubleshooting if the Xilinx Version could be implemented into the MAX technical report. 

 

In addition, the Compile Worker states that the version of Xilinx used is 12.4, regardless of whether you are using 12.4 or 12.4 SP1. It would be useful for the compile worker to note which version it is using. Specifically, often the compilation chooses the compile tools based on what it was compiled with previously. When upgrading to 12.4 SP1, the user may think the compiler automatically uses the new compile tools and has no visual cue to verify the compile tools version used. 

We have a "group" of occurrences.  We can't identity individual occurrencs easily because you can't store them in an array (where we would use indexes to identify).  When using a cluster they all get the same name (labels aren't used!) which is bug-prone.  The only workaround is to create a control cluster, and that's not a clean solution.