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Selective Chart Scale Legends

I'd like to have a way to give the FPGA on my PCIe card direct access to a block of the host PC's RAM. At the moment, the FPGA is limited to its internal RAM and whatever might be on the PCIe card. With my PCIe-7841, I have about 1MB available to the FPGA. If I need more, I have to use DMA FIFO transfers - the FPGA can use one FIFO to ask the host for some data and the host can send it to the FPGA in another FIFO. This is a lot of overhead compared with simply using a memory method node to access the FPGA RAM.

So how about a method to allocate a block of memory in the host's RAM that the FPGA can access directly over the PCIe bus with minimal involvement by the host. For simplicity, it will probably need to be limited to a contiguous block so that there are no gaps in the addresses - the FPGA would only need to know the start address and the number of bytes in the block. Ideally safeguards should be established to ensure the FPGA doesn't access memory outside the allocated block, but leaving that to the LabVIEW programmer would be fine.

The PXI-6682 is able to read time from other sources (GPS, IRIG B among others). This time can be accessed from software, but currently there is no way to synchronize the PC's system clock to the master time source. This seems like it would be relatively simple to do - indeed most competing products that read time sources are able to do it out of the box.

So my suggestion is to improve the drivers for the PXI-6682 so that it can keep the system clock synchronized when a master time source is being received.

Regular expressions in LabVIEW supports parentheses for partial matches, but this fails if your partial match is a set of operators.

Let's say I want to match "XYZ_Level" or "Level", where XYZ can be any number of characters including an empty string, the underscore must be there if XYZ is different from an empty string. These strings are valid candidates for instance:

"Level"

"_Level"

"a_Level"

"much:more_Level"

These aren't:

"aLevel"

"abc_defLevel"

I'd construct a regular expression as input to the Match Pattern primitive like this then: "(.*_)?Level", but this fails matching any of the good examples above. I think the parentheses fail to parse correctly when they contain operators? I have also tried specifying a partial match using the pipe character, like this: "(.*_|)Level", but this won't work either, probably because I need something on the right hand side of the pipe to tell the regex parser that the alternative is an empty string. An empty string is usually denoted by the epsilon character in regular expressions, but LabVIEW doesn't recognize that.

So, (unless I'm mistaken) I'd suggest LabVIEW to support parenthese in regular expressions as means of grouping anything including operators, not only substrings.

Cheers,

Steen

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Breakpoint specific case

When executing a VI state machine, especially if it called through VI server (for example as a subpanel), it would be useful to be able to set a breakpoint that triggers only on a specific case in a case structure.

You can breakpoint the entire case structure, but then you have to respond to every case.

A variation would be to be able to break after N iterations of the case.

Please note:

1. A conditional probe on the wire driving the case structure is not the same. For example in the subpanel case mentioned, the subVI and block diagram have to be closed for VI server to call the VI as a subpanel, so a breakpoint needs to be saved with the subVI when it is closed before being opened by calling code.

Please also reference this post: http://forums.ni.com/t5/LabVIEW-Idea-Exchange/Conditional-breakpoints/idi-p/1230659. It was declined because the NI moderator pointed out that you can use a conditional probe (whereas the user requested a conditional breakpoint, not a probe) but again, for the use case I mentioned above, you would need actually need a breakpoint, not a probe.

2. You can code a test on a wire into the case structure, but this requires code modification (which defeats the point of breakpoints).

3. Though you can set a breakpoint inside the case, if multiple wires enter it, you have no guarantee that in the data flow execution, the wire or object you requested will be executed first and upstream of the path you are interested in.

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I noticed an odd (undesired) behavior where my SR/FB node acted oddly.

First I created a simple !32FB node

Next I added a +1 primitive to make it a counter....

- and my data type changed! This behavior was undesired and looking through the node RCM and Properties I could not select representation

In fact I had to add a conversion. Simillarlly the same thing occured with a USR

I propose adding the ability to select representation to the RCM and Properties pages of SRs and FBNs

SR RCM FBN Property browser

If you identify some part of the Toplevel VI can be reused and you want to create subVI out of it, you will use the select the code and go to Menu bar Edit--> Create subVI.

Current behavior :

1) The connector pane is based on the no of wires required for input and output.

2) The SubVI does not have Error case.

New Idea:

The connector pane should be fixed 4x2x2x4

The code should contain Error in and error out with Error structure as shown below

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Often it is desirable to know if a control on the connector pane was wired or not. At present this can only be done by checking the value or by making the control a variant and checking if an error occurs when converting it to the proper type. Both of these have issues. Using the default value does not always work because you may need to take different action it is is truly not wired. If the control is an ENUM it would mean you have to include some value like "Invalid" in the list. This can cause confusion when using ENUM constants because it would appear that the ENUM has another value. The variant approach is problematic because it defeats automatic type checking by the compiler. It would be best if we had a simple property node on the control to indicate if it is wired or not.

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Multi Y axis XY graphs

I know that I can Have multi plots on XY but I can not find a way to have a single X axis many XY axis graph without respecifying the X axis, this is very memory and process intensive.

I would like to build an array of clusters where each cluster is a time and several variables to have an easy way to make this type of graph.

An example is an application where I had a reactor where the history was build at uneven time samples (1-5 seconds between for several days) there were 50 process variables, I would have like to build a XY graph and displayed this easily but endeded up with an array of clusters of XY arrays- not too nice.

Why isnt this represented as a single array of records (Time and vaiables) this maps to how data is sampled in the reactor.

Can this already be done?

Inspired during discussion in this nugget of Darren:

In my opinion there are a lot of good reasons to inline nearly every VI, which is reentrant. I see only three reasons for not using inlining:

1.) use recursive code (which I seldom use)
2.) call the reentrant VI dynamically (which I use more often than recursion, but still I use this seldom)
3.) you don't want to recompile every time, when you change the reentrant sub-VI

Of course you can disable inlining, if you want. It is only enabled after you set the VI reentrant. This behavior could be controlled via LabVIEW options.

Regards,

Marc

Perhaps this could be handled by having an "exit" out of a For Loop

but I think it make more sense to have the

option to have While Loop Auto - Stop if a wired array input has indexing enabled.

This would save diagram space to catch an infinite loop.

Either a right-click on the "Enable indexing" icon of the array input or a right click on the Stop if True or Stop if False icon to

change it to Purple or Orange to indicate the while loop is also enabled to stop when input array has reached its array size.

Icon on Taskbar when LV is minimized

My idea is to enable access logging for the Application Web Server.

In this way access to a web service can be analyzed which is also useful in debugging timing or performance problems of your application. To facilitate easy analysis, industry standards like the "common log format" or "combined log format" (link) should be used, then analyzer tools like AWStats can be used. The Appweb Embedded Web Server, which is the core of the Application web server, does already support logging so getting this running should be easy.

By using the VI-server reference "pane" > you will obtain a array which contains a reference for each used element. This VI-server reference can be wired in any sub-VI, to check for example the state (value) of a element. Into the respective sub-VI the array function "Array Index" can be used to check the value of the element. Everything will work fine, until you put another element into your frontpanel. At this point, LabView change the order of the reference array. Now the user wish to have a function, to edit the reference number of each element (like "Change order of elements in cluster"). The problem remains, even if the new element will be deleted.

Benchmarking Probe

How many times have you created a sequence structure with two milisecond timers around a section of code to see how fast it operates. Now the VI Profiler works great if you are only looking at whole VIs, but there are lot of cases where that the VI level is not granular enough. A great feature would be a Benchmarking Probe. It would work similar to a Breakpoint. It would have a Benchmark Probe Manager similar to the Breakpoint Manager in which you can enable/disable/delet benchmarking probes (very useful when you need to quickly see if the benchmarking code itself is adding excessive overhead).

Unlike a breakpoint or a probe, it requires two icons a Start/Stop of where you want to take a measurement. I would imagine that there would be two ways to insert the benchmark probe, one method would be similar to how insert a Breakpoint (in fact you could simply use the breakpoint tool and just add a right click option to convert to a benchmark probe). Once you clicked on the Wire that you wanted to "Start" the benchmark, the mouse icon would change to a the "Stop" benchmark icon and you would choose the place to Stop the benchmark. Of course if those two points weren't "In Place" and "Sequential" with each other, LabVIEW wouldn't allow you to place it.

Another method could be simply highlighting the area of code you want to benchmark and then right-clicking on the hgihlighted section, you would get an additional pop-up menu item for adding a benchmark, this would automatically place the two benchmark icons.

The Benchmark manager would give options of viewing the Total Time, Average Time, number of Runs in miliseconds, microseconds,etc in addtion to being able to enable disable, delete benchmarks.

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LabVIEW Idea Exchange

Specifying the decimal point character doesn't work with a time format string

Selective Chart Scale Legends

Direct PC memory access by R-series PCIe FPGA

Add capability for PXI-6682 to set system clock

Regular expression should support grouping by parentheses as well as the empty string constant

Dupicate frame for Flat sequence

Breakpoint specific case

Method to load and open the block diagram

Select represetation for Feedback Node and Shift register.

Create SubVI with VI Template

two suggestions for new controls creation in exe mode

Provide a property for controls to indicate if they were wired or not

Multi Y axis XY graphs

Inlining VI should by default be activated, if VI is made reentrant

Option to have While Loop Auto - Stop if a wired input array has indexing enabled.

Is it possile to Incorporate Boolean Toggle Function

Icon on Taskbar when LV is minimized

Enable logging in Application Web Server

VI-server reference "pane"> array of references on elements from the frontpanel

Benchmarking Probe