Parallel acquisition at 25MHz with an PXI 7854R

[FJNI]

Hello,

For an application, I need to acquire a parallel bus at 25MHz with an 7854R.

I search for information on the forum and I am few lost. I saw that we can create derivated clock on my FPGA.

I can create a 100MHz clock and use it in a SCTL to check if a rising edge appears on my clock line and acquire the data line (24 lines of data) but I don't understand what the 40MHz limitation for the DIO means.

At which rates the data is refreshed if I used a SCTL cadenced at 100MHz to read a digital input?.

Do you know if it the best way or if it is possible to acquire my bus with this hardware?

Thank you in advance for your response 

[crossrulz · Accepted solution]

The clock of the FPGA is 40MHz.  So that is the maximum rate of the inputs/outputs of the FPGA (Digital I/O).  What you could do is use a method node on the clock line to "Wait on a Rising Edge", read the data, and send the data out of a FIFO or DMA.  Put that inside of a loop and you should be good to go.