Engine Simulation Toolkit Feedback

[Sarci1]

Hi Adam,

You can take a look at the J1939 System Definition API. That may be able to provide some guidance. However, for specifics on the Engine Simulation Custom Device, you'll need to dig into the XML that's added to the *.nivssdf file when changes are made to the custom device.

Lynn

[雪飘人间and梅]

Hey Stephen:

I want to make some changes to the engine simulation toolkit custom device to meet the requirement of my customers. I don't have to chang the custom device source files in LabVIEW, what I should do is to make a FPGA project in LabVIEW ,add all the channels needed, and build a bitfile, then select the bitfile in Veristand-custom device-engine simulation toolkit-bitfile path.

Do I have an exact understanding?

Thanks!

[Sarci1]

Hello,

I don't think I fully understand the question being asked. What changes are you anticipating making? Will this just be on the FPGA or do you need additional configuration options for the user in the system definition?

Lynn

[ljcikc]

We have encountered the following error.

Could you give us some idea how to solve it?

NI VeriStand:  The custom device does not provide a valid source distribution for the target specified. Specify a different target or contact the creator of the custom device for further support.

Please see the log file below.

• Start Date: 11/4/2015 12:02 PM

• Loading System Definition file: C:\Users\Public\Documents\National Instruments\NI VeriStand 2014\Projects\Engine_Simulation_Toolkit_test\Engine_Simulation_Toolkit_test.nivssdf

• Initializing TCP subsystem...

• Starting TCP Loops...

• Connection established with target Controller.

• Preparing to synchronize with targets...

• Querying the active System Definition file from the targets...

• Stopping TCP loops.

Waiting for TCP loops to shut down...

• TCP loops shut down successfully.

• Unloading System Definition file...

• Connection with target Controller has been lost.

• Start Date: 11/4/2015 12:02 PM

• Loading System Definition file: C:\Users\Public\Documents\National Instruments\NI VeriStand 2014\Projects\Engine_Simulation_Toolkit_test\Engine_Simulation_Toolkit_test.nivssdf

• Preparing to deploy the System Definition to the targets...

• Compiling the System Definition file...

* * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * *

The VeriStand Gateway encountered an error while deploying the System Definition file.

Details:

Error -307608 occurred at Project Window.lvlib:Project Window.vi >> Project Window.lvlib:Command Loop.vi >> NI_VS Workspace ExecutionAPI.lvlib:NI VeriStand - Connect to System.vi

Possible reason(s):

NI VeriStand:  The custom device does not provide a valid source distribution for the target specified. Specify a different target or contact the creator of the custom device for further support.

=========================

NI VeriStand:  NI VeriStand Gateway.lvlib:VeriStand Server Wrapper.vi >> NI VeriStand Server.lvlib:NI VeriStand Server.vi >> NI VeriStand Server.lvlib:System Storage FG.vi >> System Storage Compiler.lvlib:System Storage To Multiple Engine Binary.vi >> Engine Data Compilation.lvlib:System Storage to Engine Binary.vi >> RT Data Management.lvlib:Populate Binary Tree Storage for RT.vi >> RT Data Management.lvlib:Populate Binary Tree.vi >> RT Data Management.lvlib:Copy Custom Device Node Properties.vi >> Custom Devices Storage.lvlib:Get Device Driver VI.vi

* * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * *

• Unloading System Definition file...

[Joel-P]

Hello ljcikc,

This error is stating that the custom device does not support the target that you are attempting to deploy to.

What device are you attempting to deploy your system definition to, and what operating system is this running? I expect that you are targeting a LinuxRT target (cRIO 903x, 906x) and the custom device does not yet support these targets.

I am already looking at what it would take to add support for these targets, but we don't have anything available right now.

Joel

[ljcikc]

I am glad you are helping me on this.

After we assigned the resource in the LabVIEW project and recompiled the bitfile, everything goes fine this time. Please see the attached picture.

However, after recompiled the bitfile we realize that we don't know how to use this tool.

Here are some screenshots for our FPGA VI block diagram.

Questions:

1. Do we need to control the "go.apu1"?

2. How do we launch the custom device and how do we know it is running?

3. Anything we are missing?

[NFT]

I see that the digital patterns are limited to 2048 transitions per cycle, which results in a maximum of 512 pulses per revolution for a 4-stroke. We have applications that use up to 3600 pulses per revolution, which would require 14400 transitions per cycle. I haven't dug very deep into the source code, but is there a specific reason 2048 transitions was chosen, and is there a relatively simple way to increase it without breaking something?

Thanks!

[NFT]

I'm having a few issues with this custom device:

1) I can't get the built 2015 version posted on this page to deploy to a cRIO-9068.

I'm getting the following error:

* * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * *

The VeriStand Gateway encountered an error while deploying the System Definition file.

Details:

Error 7 occurred at Project Window.lvlib:Project Window.vi >> Project Window.lvlib:Command Loop.vi >> NI_VS Workspace ExecutionAPI.lvlib:NI VeriStand - Connect to System.vi

Possible reason(s):

LabVIEW:  File not found. The file might be in a different location or deleted. Use the command prompt or the file explorer to verify that the path is correct.

=========================

NI-488:  Nonexistent GPIB interface.

=========================

NI VeriStand:  Open Dynamic Bitfile Reference in Engine Simulation Toolkit Engine.lvlib:Init Bitfile.vi:260001->Engine Simulation Toolkit Engine.lvlib:Initialize.vi:5890001->Engine Simulation Toolkit Engine.lvlib:RT Driver VI.vi:3170001

* * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * *

2) If I open the System Explorer, I see that there is one warning (which may or may not be related to the above error):

Name: Engine Simulation Toolkit

Path: Targets/Controller/Custom Devices/Engine Simulation Toolkit

Errors: -307832 Dependent File Property 'Driver VI Path_2' does not have a valid path.

C:\Users\Public\Documents\National Instruments\NI VeriStand 2015\Custom Devices\Engine Simulation Toolkit\c\Engine Simulation Toolkit Engine VxWorks.llb\RT Driver VI.vi

I'm not sure why it would be looking for the VxWorks LLB since I've double-checked that I have the target type set to Linux_32_ARM.

3) When I try to build the custom device from source in LabVIEW 2015, I can't get any of the Engine Release build specifications to build; they all fail with the following error:

A VI broke during the build process from being saved without a block diagram. Either open the build specification to include the block diagram of that VI or enable debugging to include the block diagrams of all VIs in the build. Report this error to National Instruments technical support.

C:\Program Files (x86)\National Instruments\LabVIEW 2015\vi.lib\Utility\error.llb\Not Found Dialog.vi

I can get the custom device to build using the Engine Debug build spec for each target, but it's missing from the Linux_32_ARM target in the project. I do have the LabVIEW FPGA Advanced Session Resources toolkit installed, and when I mass compile the project the only bad VIs listed are VI templates:

#### Starting Mass Compile: Wed, Nov 18, 2015 10:52:48 AM

  Directory: "V:\NIVS Addons\Engine-Simulation-Toolkit-Custom-Device-master\Source\Engine Simulation Toolkit Custom Device.lvproj"

  ### Bad VI:    "Engine Simulation Toolkit Engine.lvlib:Engine VI Template.vit"          Path="V:\NIVS Addons\Engine-Simulation-Toolkit-Custom-Device-master\Source\Engine\Engine VI Template.vit"

  ### Bad VI:    "Engine Simulation Toolkit Engine.lvlib:Engine VI Template.vit"          Path="V:\NIVS Addons\Engine-Simulation-Toolkit-Custom-Device-master\Source\Engine\Engine VI Template.vit"

  ### Bad VI:    "Engine Simulation Toolkit Engine.lvlib:Engine VI Template.vit"          Path="V:\NIVS Addons\Engine-Simulation-Toolkit-Custom-Device-master\Source\Engine\Engine VI Template.vit"

  ### Bad VI:    "Engine Simulation Toolkit Engine.lvlib:Engine VI Template.vit"          Path="V:\NIVS Addons\Engine-Simulation-Toolkit-Custom-Device-master\Source\Engine\Engine VI Template.vit"

  ### Bad VI:    "Engine Simulation Toolkit Engine.lvlib:Engine VI Template.vit"          Path="V:\NIVS Addons\Engine-Simulation-Toolkit-Custom-Device-master\Source\Engine\Engine VI Template.vit"

#### Finished Mass Compile: Wed, Nov 18, 2015 10:54:40 AM

However, even after re-building the custom device, I still have the same issues I've listed above.

Thanks!

Edit: I've dug into a couple of these issues and have some updates...

1) This error seems to indicate that the bitfile can't be found on the target, but I checked the target's file system and did find the bitfile at the path specified in the Main Page VI (/c/ni-rt/NIVeriStand/Custom Devices/Engine Simulation Toolkit/<bitfilename>.lvbitx). Since it appears VeriStand is capable of placing the file in this location during deployment, I'm confused as to why it has such difficulty retrieving it from the same location. Maybe something related to the way VeriStand handles Linux file paths?

3) "Not Found Dialog.vi" is a dependency of "Print CD Error.vi" in "Engine Simulation Toolkit Engine.lvlib". If I remove "Print CD Error.vi" from the RT Driver and library, "Not Found Dialog.vi" is removed from dependencies. However, when I try to build the Engine Release build spec again, I get a new error message:

A VI broke during the build process from being saved without a block diagram. Either open the build specification to include the block diagram of that VI or enable debugging to include the block diagrams of all VIs in the build. Report this error to National Instruments technical support.

C:\Program Files (x86)\National Instruments\LabVIEW 2015\vi.lib\ErrorRing\Utility\Error Code Dialog.vi

This time, I can't seem to locate "Error Code Dialog.vi" in the dependencies, and searching for it using the "Find Project Items" dialog lists no results.

The only items I see in the dependencies are:

     Custom Device API.lvlib

     Custom Device Utility Library.lvlib

     Error Cluster from Error Code.vi

     LVFPGAAdvSessionResources.lvlib

Any assistance you can provide would be greatly appreciated!

Edit 2: I think I've found the cause of the missing bitfile issue. In "Compile Engine Init.vi", the target type is being checked using "Get Target Type.vi". The enum this VI reports is missing both Linux x64 and Linux 32 ARM, so it appears to be reporting Windows by default, which causes the path to the bitfile on the PC to end up in the compiled system definition data, and the target can't locate the file because that path doesn't exist on the target. I've verified this by wiring a "VxWorks" constant to the case structure that selects the correct file path, and the target can now find the bitfile.

[Cla_Cup]

Hi Stephen,

     this is Claudio Cupini, Technical Marketing Engineer from National Instruments ITALY.

I'm trying to use the Engine Simulation Toolkit Custom Device 2015 version, but I'm experiencing a problem during the VeriStand system definition file deployment process.

In the following I attached the Deploy Status.log whithin the error description.

It seems that the RT Driver VI.vi is missing from Pharlap Engine llb (I'm working with a PXI controller). In order to try to fix the issue, I looked for the deployed pharlap llb, reaching via ftp the PXI controller.

I opened the pharlap llb and I noticed that the RT Driver VI.vi is not included. And it not included in the Pharlap llb, included in the Custom Device I downloaded as well.

I found the Custom Device Source Code, in order to try to rebuild the custom device from the LabVIEW Project, but I was unable to rebuild it because there are several dependency errors.

Could you please try to fix the issue in the built custom device I downloaded from the community (the 2015 version)?

Looking forward to reading back from you.

Kind regards.

Claudio Cupini

NI Italy

Technical Marketing Dept.

PS: I was able to use the 2014 version with VeriStand 2014, but I can't use that version since I've currently installed VeriStand 2015, and I'd like to use the newest version for an HIL demo setup.

[NFT]

I've found a bug in "Analog Replay 1.0 Init.vi":

If you look at the screenshot above, the for loop index is being multiplied by 16, then routed into both the index and length inputs of the array subset primitive. On the first iteration, both of these inputs will receive zero, preventing the first chunk of analog data from reaching the FPGA. The length input should be receiving the 16 constant directly.